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PFB_blk.vhd

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+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE work.PFB_PKG.ALL;
+USE work.POLY_FIR_PKG.ALL;
+USE work.FIVEn_DFT_PKG.ALL;
+
+ENTITY PFB_blk IS
+
+  PORT (
+    i_clk    : IN  std_logic;
+    i_data   : IN  vect_adc_data_out_pfb;
+    i_coeffs : IN  vect_polyfir_coeffs_in;
+    o_data   : OUT vect_dft_output_pfb);
+
+END ENTITY PFB_blk;
+
+ARCHITECTURE polyfir_dft OF PFB_blk IS
+
+  TYPE matrix_polyfir_data_out_transpose IS ARRAY (0 TO cst_nb_parallel_firs_dfts_pfb-1) OF vect_dft_input;
+  TYPE matrix_dft_output_pfb IS ARRAY (0 TO cst_nb_parallel_firs_dfts_pfb-1) OF vect_dft_output;
+
+  SIGNAL input_polyfir_re      : vect_adc_data_out     := (OTHERS => (OTHERS => '0'));
+  SIGNAL input_polyfir_im      : vect_adc_data_out     := (OTHERS => (OTHERS => '0'));
+  SIGNAL matrix_out_polyfir_re : matrix_fir_data_out   := (OTHERS => (OTHERS => (OTHERS => '0')));
+  SIGNAL matrix_out_polyfir_im : matrix_fir_data_out   := (OTHERS => (OTHERS => (OTHERS => '0')));
+  SIGNAL matrix_out_dft_re     : matrix_dft_output_pfb := (OTHERS => (OTHERS => (OTHERS => '0')));
+  SIGNAL matrix_out_dft_im     : matrix_dft_output_pfb := (OTHERS => (OTHERS => (OTHERS => '0')));
+  SIGNAL matrix_polyfir_out_transpose_re : matrix_polyfir_data_out_transpose := (OTHERS => (OTHERS => ( OTHERS => '0')));
+  SIGNAL matrix_polyfir_out_transpose_im : matrix_polyfir_data_out_transpose := (OTHERS => (OTHERS => ( OTHERS => '0')));
+
+BEGIN  -- ARCHITECTURE polyfir_dft
+
+
+
+  -- purpose: wiring: placing imaginary and real part in different vectors.
+  inputs_discriminating_real_imag : FOR i IN 0 TO cst_nb_samples_adc_in_pfb-1 GENERATE
+    input_polyfir_re(i) <= i_data(2*i);
+    input_polyfir_im(i) <= i_data(2*i+1);
+  END GENERATE inputs_discriminating_real_imag;
+
+
+
+  -- instanciation of 2 polyphase filter (imaginary and real part)
+  polyfir_blk_re : ENTITY work.poly_fir_blk(polyphase)
+    PORT MAP(
+      i_clk    => i_clk,
+      i_coeffs => i_coeffs,
+      i_data   => input_polyfir_re,
+      o_data   => matrix_out_polyfir_re);
+
+  polyfir_blk_im : ENTITY work.poly_fir_blk(polyphase)
+    PORT MAP(
+      i_clk    => i_clk,
+      i_coeffs => i_coeffs,
+      i_data   => input_polyfir_im,
+      o_data   => matrix_out_polyfir_im);
+
+
+
+  -- purpose: wiring: transpose the polyfir matrixes
+  transpose_for: FOR i IN 0 TO cst_nb_parallel_firs_dfts_pfb-1 GENERATE
+    transpose_data: FOR j IN 0 TO cst_nb_subfilters_pfb-1 GENERATE
+      matrix_polyfir_out_transpose_re(i)(j) <= matrix_out_polyfir_re(j)(i);
+      matrix_polyfir_out_transpose_im(i)(j) <= matrix_out_polyfir_im(j)(i);
+    END GENERATE transpose_data;
+  END GENERATE transpose_for;
+
+
+  
+  -- instanciation of cst_nb_parallel_firs_dfts_pfb dfts
+  instanciating_parallel_dfts : FOR i IN 0 TO cst_nb_parallel_firs_dfts_pfb-1 GENERATE
+    dft_inst : ENTITY work.FFT_tree(instanciating_cells)
+      GENERIC MAP (
+        nb_bits_shift_round => cst_nb_bits_shift_round_pfb)
+      PORT MAP(
+        i_clk     => i_clk,
+        i_data_re => matrix_polyfir_out_transpose_re(i),
+        i_data_im => matrix_polyfir_out_transpose_im(i),
+        o_data_re => matrix_out_dft_re(i),
+        o_data_im => matrix_out_dft_im(i)
+        );
+  END GENERATE instanciating_parallel_dfts;
+
+
+
+  -- purpose: wiring: placing imaginary part and real part every other sample
+  fill_vect_output : FOR parallel_dft_nb IN 0 TO cst_nb_parallel_firs_dfts_pfb-1 GENERATE
+    fill_line_from_matrix : FOR dft_sample_nb IN 0 TO cst_nb_subfilters_pfb-1 GENERATE
+      o_data(2*dft_sample_nb+parallel_dft_nb*2*cst_nb_subfilters_pfb)    <= matrix_out_dft_re(parallel_dft_nb)(dft_sample_nb);
+      o_data(2*dft_sample_nb+parallel_dft_nb*2*cst_nb_subfilters_pfb +1) <= matrix_out_dft_im(parallel_dft_nb)(dft_sample_nb);
+
+    END GENERATE fill_line_from_matrix;
+  END GENERATE fill_vect_output;
+
+
+END ARCHITECTURE polyfir_dft;

PFB_pkg.vhd

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+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_signed.ALL;
+USE ieee.numeric_std.ALL;
+USE work.used_functions_pkg.ALL;
+
+PACKAGE PFB_PKG IS
+
+  -- NOTES and PACKAGES INSTRUCTIONS :
+  -- please cf. sub_packages instructions
+  --
+  -- this block takes real and imaginary part every other sample, for a total
+  -- of 2*cst_nb_samples_adc_in_pfb samples in input.
+  -- does not work yet for 20 subfilters (fir to be re-tested?)
+
+  -- input
+  CONSTANT cst_w_in_pfb              : natural := 6;
+  CONSTANT cst_w_out_pfb             : natural := 6;
+  CONSTANT cst_nb_samples_adc_in_pfb : natural := 80;  -- a complete sample is a real AND an imag (both following)
+
+  -- polyphase filter
+  CONSTANT cst_w_coeffs_polyfir_pfb            : natural := 8;  -- polyfir coeffs bitwidth
+  CONSTANT cst_nb_coeffs_polyfir_pfb           : natural := 200;
+  CONSTANT cst_polyfir_downsampling_factor_pfb : natural := 8;
+
+  -- dft
+  CONSTANT cst_nb_subfilters_pfb                : natural := 10;
+  CONSTANT cst_w_precision_winograd5_coeffs_pfb : natural := 8;  -- dft winograd coeffs bitwidth
+  CONSTANT cst_w_precision_radix2_coeffs_pfb    : natural := 8;  -- dft butterfly coeffs bitwidth
+
+  CONSTANT cst_nb_bits_shift_round_pfb : natural := 19;  -- the number of MSBs to avoid (sign bits) before rounding. For cst_nb_subfilters_pfb=10, 19 works well; for cst_nb_subfilters_pfb=20, 23 should work well. See bellow for a potential correct formula, but please test for your application, don't trust this formula.
+
+  -- calculations --
+  CONSTANT cst_log2_sup_nb_coeffs_subfilter_pfb : natural := log2_sup_integer(number => cst_nb_coeffs_polyfir_pfb/cst_nb_subfilters_pfb);
+  CONSTANT cst_w_polyfir_out_dft_in_pfb         : natural := cst_w_in_pfb + cst_w_coeffs_polyfir_pfb+cst_log2_sup_nb_coeffs_subfilter_pfb;
+  CONSTANT cst_log2_nb_parallel_winograd_pfb    : natural := log2_sup_integer(number => cst_nb_subfilters_pfb/5);
+  CONSTANT cst_nb_parallel_firs_dfts_pfb        : natural := cst_nb_samples_adc_in_pfb/cst_polyfir_downsampling_factor_pfb;
+
+  --CONSTANT cst_nb_bits_shift_round_pfb : natural := 15+4*cst_log2_nb_parallel_winograd_pfb; -- potential corect formula
+
+  -- TYPES
+  SUBTYPE smpl_real_imag_adc_data_in_pfb IS std_logic_vector(cst_w_in_pfb-1 DOWNTO 0);
+  SUBTYPE smpl_real_imag_polyfir_out_dft_in_pfb IS std_logic_vector(cst_w_polyfir_out_dft_in_pfb-1 DOWNTO 0);
+  SUBTYPE smpl_real_imag_dft_out_pfb IS std_logic_vector(cst_w_out_pfb-1 DOWNTO 0);
+  --TYPE vect_fir_out_dft_in_pfb IS ARRAY (0 TO cst_nb_subfilters_pfb-1) OF smpl_real_imag_polyfir_out_dft_in_pfb;
+  TYPE vect_adc_data_out_pfb IS ARRAY (0 TO 2*cst_nb_samples_adc_in_pfb-1) OF smpl_real_imag_adc_data_in_pfb;
+
+  TYPE vect_dft_output_pfb IS ARRAY (0 TO 2*cst_nb_parallel_firs_dfts_pfb*cst_nb_subfilters_pfb-1) OF smpl_real_imag_dft_out_pfb;
+
+
+END PACKAGE PFB_PKG;
+

PFB_tb.vhd

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+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE work.PFB_PKG.ALL;
+USE work.POLY_FIR_PKG.ALL;
+USE work.FIVEn_DFT_PKG.ALL;
+USE work.simu_pkg.ALL;
+USE work.utils.ALL;
+LIBRARY std;
+USE std.textio.ALL;
+USE work.coeff_fir.ALL;
+
+ENTITY pfb_tb IS
+
+  GENERIC (
+    demi_periode : time   := 5 ns;
+-- duree de la demi periode des horloges
+    test_e       : string := "D:\Stage\ALMA_OPFB\simu\v0.1 - PFB\tb_txts_files\input.txt";
+-- fichier test contenant les echantillons d'entree
+    test_s       : string := "D:\Stage\ALMA_OPFB\simu\v0.1 - PFB\tb_txts_files\output.txt"
+-- fichier contenant les echantillons de sortie
+
+
+    );
+
+END pfb_tb;
+
+ARCHITECTURE beh OF pfb_tb IS
+  TYPE verif_vect IS ARRAY (0 TO 2*cst_nb_parallel_firs_dfts_pfb*cst_nb_subfilters_pfb-1) OF integer;
+  --TYPE partial_input_vect IS ARRAY (0 TO 9) OF smpl_in_5ndft;
+  --TYPE partial_output_vect IS ARRAY (0 TO 9) OF smpl_in_5ndft;
+  --TYPE vect_from_matrix_fir_data_out IS ARRAY (0 TO cst_nb_subfilters*cst_nb_parallel_firs-1) OF smpl_fir_data_out;
+  FILE fichier_e : text IS IN test_e;
+  FILE fichier_s : text IS IN test_s;
+  --FILE fichier_c : text IS IN test_c;
+
+  SIGNAL initialisation : std_logic;
+  SIGNAL h              : std_logic;
+  SIGNAL entree_pfb     : vect_adc_data_out_pfb  := (OTHERS => (OTHERS => '0'));
+  SIGNAL sortie_pfb     : vect_dft_output_pfb := (OTHERS => (OTHERS => '0'));
+  SIGNAL sortie_pfb_sim : vect_dft_output_pfb := (OTHERS => (OTHERS => '0'));
+  SIGNAL verif          : verif_vect;
+
+
+BEGIN  -- ARCHITECTURE beh
+
+  module_simu : ENTITY work.pfb_blk(polyfir_dft)
+    PORT MAP(h, entree_pfb, fir_coeffs_generated, sortie_pfb_sim);
+
+  horloge_entree : horloge(h, demi_periode, demi_periode);
+
+  --sortie_dft_sim_process : PROCESS(sortie_dft_sim)
+  --  VARIABLE mots_lignes : natural := 20;
+  --BEGIN
+  ----FOR k IN 0 TO mots_lignes-1 LOOP
+  ----  FOR j IN 0 TO cst_nb_subfilters-1 LOOP
+  ----    sortie_fir_sim_vect(k*mots_lignes+j) <= sortie_fir_sim(j)(k);
+  ----  END LOOP;
+  ----END LOOP;
+  --END PROCESS;
+
+  source : PROCESS
+    CONSTANT header     : natural := 1;      -- nombre de ligne d'en tête
+    CONSTANT nbr_ech    : natural := 800000;  -- nombre d'echantillons d'entree dans le fichier test 
+    CONSTANT mots_ligne : natural := 2*cst_nb_samples_adc_in_pfb;  -- nombre de mots par ligne dans le ficher
+    VARIABLE nbr_ligne  : natural := 10000;  -- nombre de lignes restant à lire dans le fichier
+    VARIABLE i          : natural := 1;
+    VARIABLE donnee     : integer;
+    VARIABLE tempo      : natural := 0;
+    VARIABLE ligne      : line;
+    VARIABLE head       : boolean := false;
+
+  BEGIN  -- PROCESS source 
+
+    WAIT UNTIL falling_edge(h);
+
+    IF head = true THEN
+      head := false;
+      FOR i IN 0 TO header-1 LOOP
+        readline(fichier_e, ligne);
+      END LOOP;
+    END IF;
+
+    IF tempo > 0 THEN                   -- temps de synchro
+      tempo := tempo -1;
+
+    ELSIF nbr_ligne > 0 THEN
+
+      readline(fichier_e, ligne);
+      nbr_ligne := nbr_ligne-1;
+
+      FOR k IN 0 TO mots_ligne -1 LOOP
+        read(ligne, donnee);
+        entree_pfb(k) <= std_logic_vector(to_signed(donnee, cst_w_in_pfb));
+      END LOOP;  -- k
+
+    END IF;
+
+  END PROCESS source;
+
+
+  test : PROCESS
+    CONSTANT header     : natural := 1;      -- nombre de ligne d'en tête
+    CONSTANT nbr_ech    : natural := 1000000;  --nombre d'echantillons d'entree dans le fichier test
+    CONSTANT mots_ligne : natural := 2*cst_nb_parallel_firs_dfts_pfb*cst_nb_subfilters_pfb;  -- nombre de mots par ligne dans le ficher
+    VARIABLE nbr_ligne  : natural := 10000;  -- nombre de lignes restant à lire dans le fichier                              
+    VARIABLE i          : natural;
+    VARIABLE donnee     : donnee_sortie;
+    VARIABLE ligne      : line;
+    VARIABLE tempo      : natural := 17;
+    VARIABLE sortie     : integer;
+    VARIABLE head       : boolean := false;
+  BEGIN  -- PROCESS test 
+
+    WAIT UNTIL falling_edge(h);
+
+
+    IF tempo > 0 THEN                   -- temps de synchro
+      tempo := tempo -1;
+      ASSERT false REPORT "Attente_2 ... " SEVERITY note;
+
+    ELSIF nbr_ligne > 0 THEN
+      readline(fichier_s, ligne);
+      nbr_ligne := nbr_ligne-1;
+
+      FOR k IN 0 TO mots_ligne-1 LOOP
+        read(ligne, donnee(k));
+        sortie        := to_integer(signed(sortie_pfb_sim(k)));
+        sortie_pfb(k) <= std_logic_vector(to_signed(donnee(k), cst_w_out_pfb));
+        verif(k)      <= sortie-donnee(k);
+        ASSERT verif(k) = 0 REPORT "Valeur dft fausse"
+          SEVERITY error;
+      --ASSERT sortie /= donnee(k) REPORT "OK"
+      --  SEVERITY note;
+      END LOOP;  -- k
+    END IF;
+
+
+
+  END PROCESS test;
+
+END ARCHITECTURE beh;

poly_fir_blk.vhd

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+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+
+
+ENTITY poly_fir_blk IS
+
+  PORT (
+    i_clk    : IN  std_logic;
+    i_coeffs : IN  vect_polyfir_coeffs_in;
+    i_data   : IN  vect_adc_data_out;
+    o_data   : OUT matrix_fir_data_out);
+
+END ENTITY poly_fir_blk;
+
+ARCHITECTURE polyphase OF poly_fir_blk IS
+
+  SIGNAL matrix3D_reg_out_simple_rif_in : matrix3D_reg_data_out := (OTHERS => (OTHERS => (OTHERS => (OTHERS => '0'))));
+  SIGNAL matrix_coeffs                  : matrix_fir_coeffs_in  := (OTHERS => (OTHERS => (OTHERS => '0')));
+  SIGNAL matrix_fir_out                 : matrix_fir_data_out   := (OTHERS => (OTHERS => (OTHERS => '0')));
+
+
+BEGIN  -- ARCHITECTURE polyphase
+
+
+
+  --purpose: fill the polyphase coefficients into a 2D matrix from the filter vector (1D)
+  fill_coeff : PROCESS(i_coeffs)        -- rearrange coeffs into a matrix
+    VARIABLE coeff_nb     : natural;
+    VARIABLE sf_coeff     : natural;
+    VARIABLE subfilter_nb : natural;
+  BEGIN
+    coeff_nb     := 0;
+    sf_coeff     := 0;
+    subfilter_nb := 0;
+    coeff_for_matrix : FOR coeff_nb IN 0 TO cst_nb_coeffs_filter_in-1 LOOP
+      matrix_coeffs(subfilter_nb)(sf_coeff) <= i_coeffs(coeff_nb);
+      subfilter_nb                          := subfilter_nb+1;
+      IF (subfilter_nb = cst_nb_subfilters) THEN
+        sf_coeff     := sf_coeff+1;
+        subfilter_nb := 0;
+      END IF;
+    END LOOP coeff_for_matrix;
+  END PROCESS fill_coeff;
+
+
+
+  -- instanciation of the shift-reg for polyphasd filter
+  shift_reg_inst : ENTITY work.POLY_SHIFT_REG(Fill_Matrix)
+    PORT MAP (i_clk  => i_clk,
+              i_data => i_data,
+              o_data => matrix3D_reg_out_simple_rif_in
+              );
+
+
+
+  -- instanciation of the (cst_nb_subfilters) subfilters
+  simple_fir_inst_loop : FOR i IN 0 TO cst_nb_subfilters-1 GENERATE
+    simple_fir_inst : ENTITY work.TREE_FIR(Simple_Fir)
+      PORT MAP(i_clk    => i_clk,
+               i_coeffs => matrix_coeffs(i),
+               i_data   => matrix3D_reg_out_simple_rif_in(i),
+               o_data   => matrix_fir_out(i)
+               );
+  END GENERATE simple_fir_inst_loop;
+
+
+
+
+  o_data <= matrix_fir_out;
+
+END ARCHITECTURE polyphase;

poly_fir_pkg.vhd

@@ -0,0 +1,108 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE ieee.std_logic_unsigned.ALL;
+USE ieee.std_logic_signed.ALL;
+USE work.PFB_PKG.ALL;
+
+PACKAGE POLY_FIR_PKG IS
+
+  -- NOTES and PACKAGE INSTRUCTIONS :
+  -- cst_downsampling_factor must be a multiplier OF cst_nb_samples_adc_in
+  -- and cst_nb_subfilters/cst_nb_samples_adc_in*cst_downsampling_factor must be an integer
+  -- with cst_downsampling_factor < or = cst_nb_subfilters.
+  --
+  -- INPUT  : vector of samples (cst_nb_samples_adc_in samples);
+  -- OUTPUT : 2D matrix of samples (matrix_fir_data_out(y)(x), with y the
+  -- subfilter number, and x the xth parallel fir);
+  --
+  -- the lower parallel fir, the older result.
+
+  -- -- CONSTANTS -- --
+
+  -- ADC
+  CONSTANT cst_w_in  : natural := cst_w_in_pfb ;    -- ADC in bitwidth
+  CONSTANT cst_w_out : natural := cst_w_polyfir_out_dft_in_pfb;
+
+  CONSTANT cst_nb_samples_adc_in : natural := cst_nb_samples_adc_in_pfb;  -- ADC in nb samples
+
+  -- FILTER
+  --coefficients
+  CONSTANT cst_w_coeff                         : natural := cst_w_coeffs_polyfir_pfb;  -- coeffs bitwidth
+  CONSTANT cst_nb_coeffs_filter_in             : natural := cst_nb_coeffs_polyfir_pfb;
+
+  -- FIR
+  CONSTANT cst_downsampling_factor : natural := cst_polyfir_downsampling_factor_pfb;
+  -- POLYPHASE FILTER
+  CONSTANT cst_nb_subfilters       : natural := cst_nb_subfilters_pfb;
+
+  -- -- CALCULATIONS -- --
+
+
+  -- SHIFT REG
+
+  CONSTANT cst_nb_coeffs_subfilter_in      : natural := cst_nb_coeffs_filter_in/cst_nb_subfilters;
+  CONSTANT cst_log2_sup_nb_coeffs_subfilter_in : natural := cst_log2_sup_nb_coeffs_subfilter_pfb;
+  CONSTANT cst_nb_samples_shiftreg_temp_in : natural := cst_nb_coeffs_subfilter_in + cst_nb_samples_adc_in/cst_downsampling_factor;
+  -- mult
+  CONSTANT cst_w_mult_out                  : natural := cst_w_coeff+cst_w_in;
+  -- adder
+  CONSTANT cst_log2_adder_stages           : natural := cst_log2_sup_nb_coeffs_subfilter_in;
+  -- fir
+  CONSTANT cst_w_fir_adder_out             : natural := cst_w_mult_out+cst_log2_adder_stages;
+  CONSTANT cst_nb_parallel_firs            : natural := cst_nb_parallel_firs_dfts_pfb;
+
+  -- TYPES
+
+  -- ADC
+  SUBTYPE smpl_adc_data_in IS smpl_real_imag_adc_data_in_pfb;
+  SUBTYPE smpl_fir_data_out IS smpl_real_imag_polyfir_out_dft_in_pfb;
+
+
+  -- SHIFT REG
+
+  TYPE vect_adc_data_out IS ARRAY (0 TO cst_nb_samples_adc_in-1) OF smpl_adc_data_in;
+  TYPE vect_fir_data_in IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_adc_data_in;
+  TYPE vect_reg_data IS ARRAY(0 TO cst_nb_samples_shiftreg_temp_in-1) OF smpl_adc_data_in;
+  TYPE matrix_reg_data IS ARRAY(0 TO cst_nb_subfilters-1) OF vect_reg_data;
+
+  TYPE matrix_reg_data_out IS ARRAY(0 TO cst_nb_parallel_firs-1) OF vect_fir_data_in;
+  TYPE matrix3D_reg_data_out IS ARRAY (0 TO cst_nb_subfilters-1) OF matrix_reg_data_out;
+
+  -- FILTER
+
+  SUBTYPE smpl_coeff IS std_logic_vector(cst_w_coeff-1 DOWNTO 0);
+
+  -- mult
+  SUBTYPE smpl_mult_data_out IS std_logic_vector(cst_w_mult_out-1 DOWNTO 0);
+  SUBTYPE smpl_mult_data_out_signed IS signed(cst_w_mult_out-1 DOWNTO 0);
+  SUBTYPE smpl_coeffs_signed IS signed(cst_w_coeff-1 DOWNTO 0);
+  SUBTYPE smpl_mult_data_in_signed IS signed(cst_w_in-1 DOWNTO 0);
+  TYPE vect_polyfir_coeffs_in IS ARRAY (0 TO cst_nb_coeffs_filter_in-1) OF smpl_coeff;
+  TYPE vect_data_mult_in_signed IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_mult_data_in_signed;
+  TYPE vect_fir_coeffs_in IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_coeff;
+  TYPE vect_mult_coeffs_signed IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_coeffs_signed;
+  TYPE vect_mult_data_out IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_mult_data_out;
+  TYPE vect_mult_data_out_signed IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_mult_data_out_signed;
+  TYPE matrix_fir_coeffs_in IS ARRAY (0 TO cst_nb_subfilters-1) OF vect_fir_coeffs_in;
+
+  -- adder
+  TYPE vect_adder_generic IS ARRAY(0 TO 2**(cst_log2_adder_stages)-1) OF std_logic_vector(cst_w_fir_adder_out-1 DOWNTO 0);
+  TYPE vect_adder_generic_signed IS ARRAY(0 TO 2**(cst_log2_adder_stages)-1) OF signed(cst_w_fir_adder_out-1 DOWNTO 0);
+  TYPE matrix_adder_generic IS ARRAY(0 TO cst_log2_adder_stages) OF vect_adder_generic;
+  TYPE matrix_adder_generic_signed IS ARRAY(0 TO cst_log2_adder_stages) OF vect_adder_generic_signed;
+
+  -- fir
+  SUBTYPE smpl_fir_adder_data_out IS std_logic_vector(cst_w_fir_adder_out-1 DOWNTO 0);
+  TYPE vect_fir_adder_data_out IS ARRAY (0 TO cst_nb_parallel_firs-1) OF smpl_fir_adder_data_out;
+  TYPE vect_fir_data_out IS ARRAY(0 TO cst_nb_parallel_firs-1) OF smpl_fir_data_out;
+
+  -- POLYPHASE FILTER
+
+  TYPE matrix_fir_data_out IS ARRAY (0 TO cst_nb_subfilters-1) OF vect_fir_data_out;
+
+
+
+
+
+END;