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pfb_5n_vhdl
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testing
Lilian RM 3 years ago
parent
8dc29bdfe5
commit
2dbb5263f9
5 changed files with 318 additions and 0 deletions
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  1. +82
    -0
      poly_shift_reg.vhd
  2. +97
    -0
      radix_2_cell.vhd
  3. +13
    -0
      simu_pkg.vhd
  4. +31
    -0
      tree_fir.vhd
  5. +95
    -0
      used_functions_pkg.vhd

+ 82
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poly_shift_reg.vhd View File

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.POLY_FIR_PKG.ALL;
ENTITY POLY_SHIFT_REG IS
PORT(i_clk : IN std_logic;
i_data : IN vect_adc_data_out;
o_data : OUT matrix3D_reg_data_out
);
END POLY_SHIFT_REG;
ARCHITECTURE Fill_Matrix OF POLY_SHIFT_REG IS
TYPE vect_i_data_temp IS ARRAY (0 TO cst_nb_subfilters-1) OF smpl_adc_data_in;
SIGNAL data_matrix : matrix3D_reg_data_out;
--SIGNAL data_temp : vect_reg_data := (OTHERS =>(OTHERS => '0'));
SIGNAL data_temp : matrix_reg_data := (OTHERS => (OTHERS => (OTHERS => '0')));
SIGNAL reg_i_data_temp : vect_i_data_temp := (OTHERS => (OTHERS => '0'));
BEGIN
-- purpose: fill a 3D matrix from a register. Each row is the input of the
-- input of a partial filter; each 2D matrix rows-columns is the input for a
-- subfilter
-- inputs: reg_i_data_temp, i_data
-- outputs: data_temp (3D matrix of std_logic_vectors)
PROCESS (i_clk) IS
VARIABLE subfilter_nb : natural := 0;
VARIABLE data_subfilter_nb : natural := 0;
BEGIN -- PROCESS
IF rising_edge(i_clk) THEN -- rising clock edge
-- add the new data to the register
FOR i IN 0 TO cst_nb_subfilters-1 LOOP -- register to store previous data
reg_i_data_temp(i) <= i_data(cst_nb_samples_adc_in-cst_nb_subfilters+i);
END LOOP; -- i
-- shifting the old samples towards reg_i_data_temp(0)
FOR i IN 0 TO cst_nb_subfilters-1 LOOP
data_temp(i)(0 TO cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs-1) <= data_temp(i)(cst_nb_parallel_firs TO cst_nb_samples_shiftreg_temp_in-1);
END LOOP; -- i
-- fill a temp 2D matrix for each subfilter (equivalent to filling a temp
-- vector for 1 filter)
parallel_fir_for : FOR parallel_fir_nb IN 0 TO cst_nb_parallel_firs-1 LOOP
fill_data_temp : FOR data_nb IN 0 TO cst_nb_subfilters-1 LOOP -- fill data and copy previous content
IF(data_nb < cst_downsampling_factor) THEN
data_temp(cst_nb_subfilters-1-((parallel_fir_nb*cst_downsampling_factor+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= i_data(cst_downsampling_factor*parallel_fir_nb+data_nb);
ELSE
IF((parallel_fir_nb*cst_downsampling_factor+data_nb)-cst_nb_subfilters < 0) THEN
data_temp(cst_nb_subfilters-1-((parallel_fir_nb*cst_downsampling_factor+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= reg_i_data_temp(data_nb);
ELSE
data_temp(cst_nb_subfilters-1-((parallel_fir_nb*cst_downsampling_factor+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= i_data(cst_downsampling_factor*parallel_fir_nb+data_nb-cst_nb_subfilters);
END IF;
END IF;
END LOOP fill_data_temp;
END LOOP parallel_fir_for; -- parallel_fir_nb
o_data <= data_matrix;
END IF;
END PROCESS;
-- purpose: wiring (filling the 3D out matrix) for each line, for each subfilter
third_dimension : FOR subfilter_nb IN 0 TO cst_nb_subfilters-1 GENERATE
second_dimension : FOR parallel_fir IN 0 TO cst_nb_parallel_firs-1 GENERATE
first_dimension : FOR data_nb IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
data_matrix(subfilter_nb)(parallel_fir)(data_nb) <= data_temp(subfilter_nb)(data_nb+parallel_fir);
END GENERATE first_dimension; -- data_nb
END GENERATE second_dimension; -- parallel_fir
END GENERATE third_dimension; -- subfilter_nb
END Fill_Matrix;

+ 97
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radix_2_cell.vhd View File

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_signed.ALL;
USE ieee.numeric_std.ALL;
USE work.FIVEn_DFT_PKG.ALL;
ENTITY radix_2_cell_winograd IS
GENERIC(
w_in : natural
);
PORT(
i_clk : std_logic;
i_cos : smpl_cos_sin_wb;
i_sin : smpl_cos_sin_wb;
i_data1_re : IN smpl_out_radix2;
i_data1_im : IN smpl_out_radix2;
i_data2_re : IN smpl_out_radix2;
i_data2_im : IN smpl_out_radix2;
o_data1_re : OUT smpl_out_radix2;
o_data1_im : OUT smpl_out_radix2;
o_data2_re : OUT smpl_out_radix2;
o_data2_im : OUT smpl_out_radix2
);
END radix_2_cell_winograd;
ARCHITECTURE radix2 OF radix_2_cell_winograd IS
TYPE vect_result_multiply IS ARRAY (0 TO 1) OF std_logic_vector(w_in + cst_w_precision_radix2_coeffs_5ndft-2 DOWNTO 0);
SIGNAL signed_data_im : smpl_out_winograd5_signed_5ndft := (OTHERS => '0');
SIGNAL signed_data_re : smpl_out_winograd5_signed_5ndft := (OTHERS => '0');
SIGNAL multiply_by_2_power_cst_w_precision : std_logic_vector(cst_w_precision_radix2_coeffs_5ndft-3 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_matrix_im : matrix_radix2_cell := (OTHERS => (OTHERS => (OTHERS => '0')));
SIGNAL data_matrix_re : matrix_radix2_cell := (OTHERS => (OTHERS => (OTHERS => '0')));
SIGNAL data_vect_result_mult_re : vect_result_multiply := (OTHERS => (OTHERS => '0'));
SIGNAL data_vect_result_mult_im : vect_result_multiply := (OTHERS => (OTHERS => '0'));
BEGIN
-- assign block inputs and outputs their corresponding matrix columns
data_matrix_re(0)(0) <= i_data1_re;
data_matrix_re(1)(0) <= i_data2_re;
data_matrix_im(0)(0) <= i_data1_im;
data_matrix_im(1)(0) <= i_data2_im;
o_data1_re <= data_matrix_re(0)(3);
o_data2_re <= data_matrix_re(1)(3);
o_data1_im <= data_matrix_im(0)(3);
o_data2_im <= data_matrix_im(1)(3);
--instanciating the MULT_BLK_5nDFT(Mult_Path)
mult_inst1 : ENTITY work.MULT_BLK_5nDFT(Mult_Path)
GENERIC MAP(
w_in => w_in,
w_mult => cst_w_precision_radix2_coeffs_5ndft
)
PORT MAP(i_clk => i_clk,
i_data_re => data_matrix_re(1)(0),
i_data_im => data_matrix_im(1)(0),
i_cos => i_cos,
i_sin => i_sin,
o_data_re => data_matrix_re(1)(2),
o_data_im => data_matrix_im(1)(2)
);
-- purpose: calculating the multiplication and the 2 additions/substractions.
-- The multiplication per 1 in the top of the butterfly is replaced by a
-- shift with 0s towards the MSBs
-- inputs: data_matrix_im(x)(0), data_matrix_re(x)(0)
-- outputs: data_matrix_im(x)(3), data_matrix_re(x)(3)
radix2_structure : PROCESS(i_clk)
BEGIN
IF(rising_edge(i_clk)) THEN
-- mult per 1 (top)
data_matrix_im(0)(1)(w_in+cst_w_precision_radix2_coeffs_5ndft DOWNTO 0) <= data_matrix_im(0)(0)(w_in-1)&data_matrix_im(0)(0)(w_in-1)&data_matrix_im(0)(0)(w_in-1)&data_matrix_im(0)(0)(w_in-1 DOWNTO 0)&multiply_by_2_power_cst_w_precision;
data_matrix_re(0)(1)(w_in+cst_w_precision_radix2_coeffs_5ndft DOWNTO 0) <= data_matrix_re(0)(0)(w_in-1)&data_matrix_re(0)(0)(w_in-1)&data_matrix_re(0)(0)(w_in-1)&data_matrix_re(0)(0)(w_in-1 DOWNTO 0)&multiply_by_2_power_cst_w_precision;
data_matrix_im(0)(2) <= data_matrix_im(0)(1);
data_matrix_re(0)(2) <= data_matrix_re(0)(1);
-- mult (down) : see mult_blk instanciation
--add
data_matrix_re(0)(3)(w_in+cst_w_precision_radix2_coeffs_5ndft+1 DOWNTO 0) <= std_logic_vector(unsigned(signed(data_matrix_re(0)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft)&data_matrix_re(0)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft DOWNTO 0))+signed(data_matrix_re(1)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft)&data_matrix_re(1)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft DOWNTO 0))));
data_matrix_re(1)(3)(w_in+cst_w_precision_radix2_coeffs_5ndft+1 DOWNTO 0) <= std_logic_vector(unsigned(signed(data_matrix_re(0)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft)&data_matrix_re(0)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft DOWNTO 0))-signed(data_matrix_re(1)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft)&data_matrix_re(1)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft DOWNTO 0))));
data_matrix_im(0)(3)(w_in+cst_w_precision_radix2_coeffs_5ndft+1 DOWNTO 0) <= std_logic_vector(unsigned(signed(data_matrix_im(0)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft)&data_matrix_im(0)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft DOWNTO 0))+signed(data_matrix_im(1)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft)&data_matrix_im(1)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft DOWNTO 0))));
data_matrix_im(1)(3)(w_in+cst_w_precision_radix2_coeffs_5ndft+1 DOWNTO 0) <= std_logic_vector(unsigned(signed(data_matrix_im(0)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft)&data_matrix_im(0)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft DOWNTO 0))-signed(data_matrix_im(1)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft)&data_matrix_im(1)(2)(w_in+cst_w_precision_radix2_coeffs_5ndft DOWNTO 0))));
END IF;
END PROCESS;
END radix2;

+ 13
- 0
simu_pkg.vhd View File

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.PFB_PKG.ALL;
PACKAGE simu_pkg IS
TYPE donnee_sortie IS ARRAY (0 TO 2*cst_nb_parallel_firs_dfts_pfb*cst_nb_subfilters_pfb-1) OF integer;
CONSTANT w_x_simu : natural := 4;
END;

+ 31
- 0
tree_fir.vhd View File

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.POLY_FIR_PKG.ALL;
ENTITY TREE_FIR IS
PORT( i_clk : IN std_logic;
i_coeffs : IN vect_fir_coeffs_in;
i_data : IN matrix_reg_data_out;
o_data : OUT vect_fir_data_out
);
END TREE_FIR;
ARCHITECTURE Simple_Fir OF TREE_FIR IS
SIGNAL partial_fir_out : vect_fir_adder_data_out := (OTHERS => (OTHERS => '0'));
BEGIN
-- purpose: wiring: instanciation of each partial FIR to make 1 FIR
partial_fir_for : FOR i IN 0 TO cst_nb_parallel_firs-1 GENERATE
partial_fir_inst : ENTITY work.PARTIAL_FIR(Adder_Tree)
PORT MAP( i_clk => i_clk,
i_coeffs => i_coeffs,
i_data => i_data(i),
o_data => partial_fir_out(i)
);
o_data(i)<= partial_fir_out(i)(cst_w_fir_adder_out-1 DOWNTO cst_w_fir_adder_out-cst_w_out);
END GENERATE partial_fir_for;
END Simple_Fir;

+ 95
- 0
used_functions_pkg.vhd View File

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_signed.ALL;
USE ieee.numeric_std.ALL;
PACKAGE used_functions_pkg IS
FUNCTION log2_sup_integer (number : natural) RETURN natural;
FUNCTION log2_inf_integer (number : natural) RETURN natural;
END PACKAGE;
PACKAGE BODY used_functions_pkg IS
--functions
FUNCTION log2_sup_integer (number : natural) RETURN natural IS
VARIABLE result : natural;
BEGIN
IF(number <= 1) THEN
result := 0;
ELSIF(number = 2) THEN
result := 1;
ELSIF(number > 2 AND number <= 4) THEN
result := 2;
ELSIF(number > 4 AND number <= 8) THEN
result := 3;
ELSIF(number > 8 AND number <= 16) THEN
result := 4;
ELSIF(number > 16 AND number <= 32) THEN
result := 5;
ELSIF(number > 32 AND number <= 64) THEN
result := 6;
ELSIF(number > 64 AND number <= 128) THEN
result := 7;
ELSIF(number > 128 AND number <= 256) THEN
result := 8;
ELSIF(number > 256 AND number <= 512) THEN
result := 9;
ELSIF(number > 512 AND number <= 1024) THEN
result := 10;
ELSIF(number > 1024 AND number <= 2048) THEN
result := 11;
ELSIF(number > 2048 AND number <= 4096) THEN
result := 12;
ELSIF(number > 4096 AND number <= 8192) THEN
result := 13;
ELSIF(number > 8192 AND number <= 16384) THEN
result := 14;
ELSIF(number > 16384 AND number <= 32768) THEN
result := 15;
END IF;
RETURN result;
END FUNCTION;
FUNCTION log2_inf_integer (number : natural) RETURN natural IS
VARIABLE result : natural;
BEGIN
IF(number < 2) THEN
result := 0;
ELSIF(number >= 2 AND number < 4) THEN
result := 1;
ELSIF(number >= 4 AND number < 8) THEN
result := 2;
ELSIF(number >= 8 AND number < 16) THEN
result := 3;
ELSIF(number >= 16 AND number < 32) THEN
result := 4;
ELSIF(number >= 32 AND number < 64) THEN
result := 5;
ELSIF(number >= 64 AND number < 128) THEN
result := 6;
ELSIF(number >= 128 AND number < 256) THEN
result := 7;
ELSIF(number >= 256 AND number < 512) THEN
result := 8;
ELSIF(number >= 512 AND number < 1024) THEN
result := 9;
ELSIF(number >= 1024 AND number < 2048) THEN
result := 10;
ELSIF(number >= 2048 AND number < 4096) THEN
Result := 11;
ELSIF(Number >= 4096 AND number < 8192) THEN
result := 12;
ELSIF(number >= 8192 AND number < 16384) THEN
result := 13;
ELSIF(number >= 16384 AND number < 32768) THEN
result := 14;
END IF;
RETURN result;
END FUNCTION;
END PACKAGE BODY used_functions_pkg;

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