@@ -0,0 +1,57 @@ | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
USE ieee.numeric_std.ALL; | |||||
USE work.GENERAL_INCLUDES.ALL; | |||||
ENTITY PARTIAL_FIR IS | |||||
PORT( i_clk : IN std_logic; | |||||
i_coeffs : IN vect_fir_coeffs_in; | |||||
i_data : IN vect_fir_data_in; | |||||
o_data : OUT smpl_fir_adder_data_out | |||||
); | |||||
END PARTIAL_FIR; | |||||
ARCHITECTURE Adder_Tree OF PARTIAL_FIR IS | |||||
SIGNAL matrix_adder_tree : matrix_adder_generic := (OTHERS => (OTHERS => (OTHERS => '0'))); | |||||
SIGNAL matrix_adder_tree_signed : matrix_adder_generic_signed := (OTHERS => (OTHERS => (OTHERS => '0'))); | |||||
SIGNAL vect_i_coeffs : vect_fir_coeffs_in; | |||||
SIGNAL mult_out : vect_mult_data_out := (OTHERS => (OTHERS => '0')); | |||||
BEGIN | |||||
in_assignment : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE | |||||
vect_i_coeffs(i) <= i_coeffs(cst_nb_coeffs_subfilter_in-1-i); | |||||
END GENERATE in_assignment; | |||||
mult_inst : ENTITY work.MULT_BLK(Mult_Path) | |||||
PORT MAP( i_clk => i_clk, | |||||
i_data => i_data, | |||||
i_coeffs => vect_i_coeffs, | |||||
o_data => mult_out(0 TO cst_nb_coeffs_subfilter_in-1) | |||||
); | |||||
mult_out_wire : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE | |||||
matrix_adder_tree(0)(i)(cst_w_mult_out-1 DOWNTO 0) <= mult_out(i)(cst_w_mult_out-1 DOWNTO 0); | |||||
END GENERATE mult_out_wire; | |||||
stages_loop : FOR stage IN 1 TO cst_log2_adder_stages GENERATE | |||||
cell_loops : FOR cell IN 0 TO 2**(cst_log2_adder_stages-stage)-1 GENERATE | |||||
matrix_adder_tree_signed(stage)((2**stage)*cell)(cst_w_mult_out+stage-1 DOWNTO 0) <= signed(matrix_adder_tree(stage-1)((2**stage)*cell)(cst_w_mult_out+stage-2)&matrix_adder_tree(stage-1)((2**stage)*cell)(cst_w_mult_out+stage-2 DOWNTO 0))+signed(matrix_adder_tree(stage-1)((2**(stage-1))*(2*cell+1))(cst_w_mult_out+stage-2)&matrix_adder_tree(stage-1)((2**(stage-1))*(2*cell+1))(cst_w_mult_out+stage-2 DOWNTO 0)); | |||||
matrix_adder_tree(stage)((2**stage)*cell)(cst_w_mult_out+stage-1 DOWNTO 0) <= std_logic_vector(unsigned(matrix_adder_tree_signed(stage)((2**stage)*cell)(cst_w_mult_out+stage-1 DOWNTO 0))); | |||||
END GENERATE cell_loops; | |||||
END GENERATE stages_loop; | |||||
adder_tree_process : PROCESS(i_clk) | |||||
BEGIN | |||||
IF(rising_edge(i_clk)) THEN | |||||
o_data <= matrix_adder_tree(cst_log2_adder_stages)(0); | |||||
END IF; | |||||
END PROCESS; | |||||
END Adder_Tree; |
@@ -0,0 +1,42 @@ | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
USE work.GENERAL_INCLUDES.ALL; | |||||
ENTITY SHIFT_REG IS | |||||
GENERIC(nb_samples_temp : natural := cst_nb_samples_shiftreg_temp_in; | |||||
nb_samples_line_matrix : natural := cst_nb_coeffs_subfilter_in | |||||
); | |||||
PORT(i_clk : IN std_logic; | |||||
i_data : IN vect_adc_data_out; | |||||
o_data : OUT matrix_reg_data_out | |||||
); | |||||
END SHIFT_REG; | |||||
ARCHITECTURE Fill_Matrix OF SHIFT_REG IS | |||||
SIGNAL data_matrix : matrix_reg_data_out; | |||||
SIGNAL data_clk : vect_reg_data; | |||||
BEGIN | |||||
PROCESS(i_clk) IS | |||||
BEGIN | |||||
IF(rising_edge(i_clk)) THEN | |||||
data_clk(0 TO nb_samples_temp-cst_nb_samples_adc_in-1) <= data_clk(cst_nb_samples_adc_in TO nb_samples_temp-1); | |||||
FOR i IN 0 TO cst_nb_samples_adc_in-1 LOOP | |||||
data_clk(nb_samples_temp-cst_nb_samples_adc_in+i) <= i_data(i); | |||||
END LOOP; -- i | |||||
FOR lines IN 0 TO cst_nb_samples_adc_in-1 LOOP | |||||
-- the smaller line, the older samples | |||||
FOR samples IN 0 TO nb_samples_line_matrix-1 LOOP | |||||
data_matrix(lines)(samples) <= data_clk(lines+samples); | |||||
END LOOP; | |||||
END LOOP; | |||||
ELSE | |||||
data_clk <= data_clk; | |||||
END IF; | |||||
o_data <= data_matrix; | |||||
END PROCESS; | |||||
END Fill_Matrix; |
@@ -0,0 +1,13 @@ | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
USE ieee.numeric_std.ALL; | |||||
USE work.general_includes.ALL; | |||||
PACKAGE simu_pkg IS | |||||
TYPE donnee_sortie IS ARRAY (0 TO cst_nb_samples_adc_in-1) OF integer; | |||||
CONSTANT w_x_simu : natural := 4; | |||||
END; |
@@ -0,0 +1,40 @@ | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
USE work.GENERAL_INCLUDES.ALL; | |||||
ENTITY TREE_FIR IS | |||||
PORT( i_clk : IN std_logic; | |||||
i_coeffs : IN vect_fir_coeffs_in; | |||||
i_data : IN vect_adc_data_out; | |||||
o_data : OUT vect_fir_data_out | |||||
); | |||||
END TREE_FIR; | |||||
ARCHITECTURE Shift_Reg_Fir OF TREE_FIR IS | |||||
SIGNAL matrix_data_reg_out_mult_in : matrix_reg_data_out := (OTHERS => (OTHERS => (OTHERS => '0'))); | |||||
SIGNAL partial_fir_out : vect_fir_adder_data_out := (OTHERS => (OTHERS => '0')); | |||||
BEGIN | |||||
shift_reg_inst : ENTITY work.SHIFT_REG(Fill_Matrix) | |||||
GENERIC MAP(nb_samples_temp => cst_nb_samples_shiftreg_temp_in, | |||||
nb_samples_line_matrix => cst_nb_coeffs_subfilter_in | |||||
) | |||||
PORT MAP( i_clk => i_clk, | |||||
i_data => i_data, | |||||
o_data => matrix_data_reg_out_mult_in | |||||
); | |||||
partial_fir_for : FOR i IN 0 TO cst_nb_samples_adc_in-1 GENERATE | |||||
partial_fir_inst : ENTITY work.PARTIAL_FIR(Adder_Tree) | |||||
PORT MAP( i_clk => i_clk, | |||||
i_coeffs => i_coeffs, | |||||
i_data => matrix_data_reg_out_mult_in(i), | |||||
o_data => partial_fir_out(i) | |||||
); | |||||
o_data(i)<= partial_fir_out(i)(cst_w_fir_adder_out-1 DOWNTO cst_w_fir_adder_out-cst_w_out); | |||||
END GENERATE partial_fir_for; | |||||
END Shift_Reg_Fir; |
@@ -0,0 +1,33 @@ | |||||
-- *********************** Divers fonction utiles *************************** | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
PACKAGE utils IS | |||||
PROCEDURE horloge ( SIGNAL h: OUT std_logic; th, tb : time); | |||||
PROCEDURE horloge_retard ( SIGNAL h : OUT std_logic; periode : time ; | |||||
retard : time); | |||||
END utils; | |||||
--------------------------------------------------- | |||||
PACKAGE BODY utils IS | |||||
PROCEDURE horloge ( SIGNAL h : OUT std_logic; th, tb : time) IS | |||||
BEGIN | |||||
LOOP | |||||
h <= '0', '1' AFTER tb; | |||||
WAIT FOR tb + th ; | |||||
END LOOP; | |||||
END; | |||||
PROCEDURE horloge_retard ( SIGNAL h : OUT std_logic; periode : time ; | |||||
retard : time) IS | |||||
BEGIN | |||||
h <= '0'; | |||||
WAIT FOR retard; | |||||
LOOP | |||||
h <= '1' , '0' AFTER periode/2 ; | |||||
WAIT FOR periode; | |||||
END LOOP; | |||||
END; | |||||
END utils; |