A simple vhdl fir description.
Du kan inte välja fler än 25 ämnen Ämnen måste starta med en bokstav eller siffra, kan innehålla bindestreck ('-') och vara max 35 tecken långa.

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  1. -- *********************** Divers fonction utiles ***************************
  2. LIBRARY ieee;
  3. USE ieee.std_logic_1164.ALL;
  4. PACKAGE utils IS
  5. PROCEDURE horloge ( SIGNAL h: OUT std_logic; th, tb : time);
  6. PROCEDURE horloge_retard ( SIGNAL h : OUT std_logic; periode : time ;
  7. retard : time);
  8. END utils;
  9. ---------------------------------------------------
  10. PACKAGE BODY utils IS
  11. PROCEDURE horloge ( SIGNAL h : OUT std_logic; th, tb : time) IS
  12. BEGIN
  13. LOOP
  14. h <= '0', '1' AFTER tb;
  15. WAIT FOR tb + th ;
  16. END LOOP;
  17. END;
  18. PROCEDURE horloge_retard ( SIGNAL h : OUT std_logic; periode : time ;
  19. retard : time) IS
  20. BEGIN
  21. h <= '0';
  22. WAIT FOR retard;
  23. LOOP
  24. h <= '1' , '0' AFTER periode/2 ;
  25. WAIT FOR periode;
  26. END LOOP;
  27. END;
  28. END utils;