pfb_5n_vhdl/polyphase_filter/poly_fir_blk__wires.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.POLY_FIR_PKG.ALL;



ENTITY tree_firs IS

  PORT (
    i_clk : IN std_logic;
    i_matrix3D_reg_out : IN  matrix3D_reg_data_out;
    i_coeffs : IN matrix_fir_coeffs_in;
    o_data : OUT matrix_fir_data_out := (OTHERS => (OTHERS => (OTHERS => '0')))
    );

END ENTITY tree_firs;

ARCHITECTURE wires OF tree_firs IS


BEGIN

  -- instanciation of the cst_nb_subfilters subfilters
  simple_fir_inst_loop : FOR i IN 0 TO cst_nb_subfilters-1 GENERATE
    simple_fir_inst : ENTITY work.TREE_FIR(Simple_Fir)
      PORT MAP(i_clk    => i_clk,
               i_coeffs => i_coeffs(i),
               i_data   => i_matrix3D_reg_out(i),
               o_data   => o_data(i)
               );
  END GENERATE simple_fir_inst_loop;





END ARCHITECTURE wires;