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@@ -1,31 +0,0 @@ |
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE work.POLY_FIR_PKG.ALL;
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ENTITY TREE_FIR IS
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PORT( i_clk : IN std_logic;
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i_coeffs : IN vect_fir_coeffs_in;
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i_data : IN matrix_reg_data_out;
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o_data : OUT vect_fir_data_out
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);
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END TREE_FIR;
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ARCHITECTURE Simple_Fir OF TREE_FIR IS
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SIGNAL partial_fir_out : vect_fir_adder_data_out := (OTHERS => (OTHERS => '0'));
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BEGIN
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-- purpose: wiring: instanciation of each partial FIR to make 1 FIR
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partial_fir_for : FOR i IN 0 TO cst_nb_parallel_firs-1 GENERATE
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partial_fir_inst : ENTITY work.PARTIAL_FIR(Adder_Tree)
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PORT MAP( i_clk => i_clk,
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i_coeffs => i_coeffs,
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i_data => i_data(i),
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o_data => partial_fir_out(i)
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);
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o_data(i)<= partial_fir_out(i)(cst_w_fir_adder_out-1 DOWNTO cst_w_fir_adder_out-cst_w_out);
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END GENERATE partial_fir_for;
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END Simple_Fir;
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