From 4d614007771fd4af4b53115de42ad106ca6b465a Mon Sep 17 00:00:00 2001 From: Lilian RM Date: Wed, 29 Jul 2020 08:41:48 +0100 Subject: [PATCH] =?UTF-8?q?Transf=C3=A9rer=20les=20fichiers=20vers=20'poly?= =?UTF-8?q?phase=5Ffilter'?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit polyphase_filter v0.2 --- polyphase_filter/poly_fir_pkg.vhd | 200 +++++++++++++++++++++++++++ polyphase_filter/poly_shift_reg2.vhd | 79 +++++++++++ polyphase_filter/tree_fir.vhd | 31 +++++ 3 files changed, 310 insertions(+) create mode 100644 polyphase_filter/poly_fir_pkg.vhd create mode 100644 polyphase_filter/poly_shift_reg2.vhd create mode 100644 polyphase_filter/tree_fir.vhd diff --git a/polyphase_filter/poly_fir_pkg.vhd b/polyphase_filter/poly_fir_pkg.vhd new file mode 100644 index 0000000..ff14728 --- /dev/null +++ b/polyphase_filter/poly_fir_pkg.vhd @@ -0,0 +1,200 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +USE ieee.std_logic_unsigned.ALL; +USE ieee.std_logic_signed.ALL; + +PACKAGE POLY_FIR_PKG IS + + -- NOTES and PACKAGE INSTRUCTIONS : + -- cst_downsampling_factor must be a multiplier OF cst_nb_samples_adc_in + -- and cst_nb_subfilters/cst_nb_samples_adc_in*cst_downsampling_factor must be an integer + -- with cst_downsampling_factor < or = cst_nb_subfilters. + -- + -- INPUT : vector of samples (cst_nb_samples_adc_in samples); + -- OUTPUT : 2D matrix of samples (matrix_fir_data_out(y)(x), with y the + -- subfilter number, and x the xth parallel fir); + -- + -- the lower parallel fir, the older result. + + + + FUNCTION log2_sup_integer (number : natural) RETURN natural; + FUNCTION log2_inf_integer (number : natural) RETURN natural; + + -- -- CONSTANTS -- -- + + -- ADC + CONSTANT cst_w_in : natural := 6; -- ADC in bitwidth + + CONSTANT cst_nb_samples_adc_in : natural := 80; -- ADC in nb samples + + -- FILTER + --coefficients + CONSTANT cst_w_coeff : natural := 8; -- coeffs bitwidth + CONSTANT cst_nb_coeffs_filter_in : natural := 7*20; + CONSTANT cst_log2_sup_nb_coeffs_subfilter_in : natural := 3; + + -- FIR + CONSTANT cst_downsampling_factor : natural := 8; + -- POLYPHASE FILTER + CONSTANT cst_nb_subfilters : natural := 20; + + + -- -- CALCULATIONS -- -- + + CONSTANT cst_w_out : natural := cst_w_in + cst_w_coeff+cst_log2_sup_nb_coeffs_subfilter_in; + + -- SHIFT REG + + CONSTANT cst_nb_coeffs_subfilter_in : natural := cst_nb_coeffs_filter_in/cst_nb_subfilters; + CONSTANT cst_nb_samples_shiftreg_temp_in : natural := cst_nb_coeffs_subfilter_in + cst_nb_samples_adc_in/cst_downsampling_factor; + -- mult + CONSTANT cst_w_mult_out : natural := cst_w_coeff+cst_w_in; + -- adder + CONSTANT cst_log2_adder_stages : natural := cst_log2_sup_nb_coeffs_subfilter_in; + -- fir + CONSTANT cst_w_fir_adder_out : natural := cst_w_mult_out+cst_log2_adder_stages; + CONSTANT cst_nb_parallel_firs : natural := cst_nb_samples_adc_in/cst_downsampling_factor; + + -- TYPES + + -- ADC + SUBTYPE smpl_adc_data_in IS std_logic_vector(cst_w_in-1 DOWNTO 0); + SUBTYPE smpl_fir_data_out IS std_logic_vector(cst_w_out-1 DOWNTO 0); + + + -- SHIFT REG + + TYPE vect_adc_data_out IS ARRAY (0 TO cst_nb_samples_adc_in-1) OF smpl_adc_data_in; + TYPE vect_fir_data_in IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_adc_data_in; + TYPE vect_reg_data IS ARRAY(0 TO cst_nb_samples_shiftreg_temp_in-1) OF smpl_adc_data_in; + TYPE matrix_reg_data IS ARRAY(0 TO cst_nb_subfilters-1) OF vect_reg_data; + + TYPE matrix_reg_data_out IS ARRAY(0 TO cst_nb_parallel_firs-1) OF vect_fir_data_in; + TYPE matrix3D_reg_data_out IS ARRAY (0 TO cst_nb_subfilters-1) OF matrix_reg_data_out; + + -- FILTER + + SUBTYPE smpl_coeff IS std_logic_vector(cst_w_coeff-1 DOWNTO 0); + + -- mult + SUBTYPE smpl_mult_data_out IS std_logic_vector(cst_w_mult_out-1 DOWNTO 0); + SUBTYPE smpl_mult_data_out_signed IS signed(cst_w_mult_out-1 DOWNTO 0); + SUBTYPE smpl_coeffs_signed IS signed(cst_w_coeff-1 DOWNTO 0); + SUBTYPE smpl_mult_data_in_signed IS signed(cst_w_in-1 DOWNTO 0); + TYPE vect_polyfir_coeffs_in IS ARRAY (0 TO cst_nb_coeffs_filter_in-1) OF smpl_coeff; + TYPE vect_data_mult_in_signed IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_mult_data_in_signed; + TYPE vect_fir_coeffs_in IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_coeff; + TYPE vect_mult_coeffs_signed IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_coeffs_signed; + TYPE vect_mult_data_out IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_mult_data_out; + TYPE vect_mult_data_out_signed IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_mult_data_out_signed; + TYPE matrix_fir_coeffs_in IS ARRAY (0 TO cst_nb_subfilters-1) OF vect_fir_coeffs_in; + + -- adder + SUBTYPE smpl_adder_generic IS std_logic_vector(cst_w_fir_adder_out-1 DOWNTO 0); + SUBTYPE smpl_adder_generic_signed IS signed(cst_w_fir_adder_out-1 DOWNTO 0); + TYPE vect_adder_generic IS ARRAY(0 TO 2**(cst_log2_adder_stages)-1) OF smpl_adder_generic; + TYPE vect_adder_generic_signed IS ARRAY(0 TO 2**(cst_log2_adder_stages)-1) OF smpl_adder_generic_signed; + TYPE matrix_adder_generic IS ARRAY(0 TO cst_log2_adder_stages) OF vect_adder_generic; + TYPE matrix_adder_generic_signed IS ARRAY(0 TO cst_log2_adder_stages) OF vect_adder_generic_signed; + + -- fir + SUBTYPE smpl_fir_adder_data_out IS std_logic_vector(cst_w_fir_adder_out-1 DOWNTO 0); + TYPE vect_fir_adder_data_out IS ARRAY (0 TO cst_nb_parallel_firs-1) OF smpl_fir_adder_data_out; + TYPE vect_fir_data_out IS ARRAY(0 TO cst_nb_parallel_firs-1) OF smpl_fir_data_out; + + -- POLYPHASE FILTER + + TYPE matrix_fir_data_out IS ARRAY (0 TO cst_nb_subfilters-1) OF vect_fir_data_out; + -- TYPE matrix_coeffs_polyphase_filter IS array(0 to cst_nb_subfilters) OF vect_mult_coeffs; + + + + + +END; + +PACKAGE BODY POLY_FIR_PKG IS + + + --functions + FUNCTION log2_sup_integer (number : natural) RETURN natural IS + VARIABLE result : natural; + BEGIN + + IF(number <= 1) THEN + result := 0; + ELSIF(number = 2) THEN + result := 1; + ELSIF(number > 2 AND number <= 4) THEN + result := 2; + ELSIF(number > 4 AND number <= 8) THEN + result := 3; + ELSIF(number > 8 AND number <= 16) THEN + result := 4; + ELSIF(number > 16 AND number <= 32) THEN + result := 5; + ELSIF(number > 32 AND number <= 64) THEN + result := 6; + ELSIF(number > 64 AND number <= 128) THEN + result := 7; + ELSIF(number > 128 AND number <= 256) THEN + result := 8; + ELSIF(number > 256 AND number <= 512) THEN + result := 9; + ELSIF(number > 512 AND number <= 1024) THEN + result := 10; + ELSIF(number > 1024 AND number <= 2048) THEN + result := 11; + ELSIF(number > 2048 AND number <= 4096) THEN + result := 12; + ELSIF(number > 4096 AND number <= 8192) THEN + result := 13; + ELSIF(number > 8192 AND number <= 16384) THEN + result := 14; + ELSIF(number > 16384 AND number <= 32768) THEN + result := 15; + END IF; + RETURN result; + END FUNCTION; + + FUNCTION log2_inf_integer (number : natural) RETURN natural IS + VARIABLE result : natural; + BEGIN + + IF(number < 2) THEN + result := 0; + ELSIF(number >= 2 AND number < 4) THEN + result := 1; + ELSIF(number >= 4 AND number < 8) THEN + result := 2; + ELSIF(number >= 8 AND number < 16) THEN + result := 3; + ELSIF(number >= 16 AND number < 32) THEN + result := 4; + ELSIF(number >= 32 AND number < 64) THEN + result := 5; + ELSIF(number >= 64 AND number < 128) THEN + result := 6; + ELSIF(number >= 128 AND number < 256) THEN + result := 7; + ELSIF(number >= 256 AND number < 512) THEN + result := 8; + ELSIF(number >= 512 AND number < 1024) THEN + result := 9; + ELSIF(number >= 1024 AND number < 2048) THEN + result := 10; + ELSIF(number >= 2048 AND number < 4096) THEN + Result := 11; + ELSIF(Number >= 4096 AND number < 8192) THEN + result := 12; + ELSIF(number >= 8192 AND number < 16384) THEN + result := 13; + ELSIF(number >= 16384 AND number < 32768) THEN + result := 14; + END IF; + RETURN result; + END FUNCTION; + +END PACKAGE BODY; diff --git a/polyphase_filter/poly_shift_reg2.vhd b/polyphase_filter/poly_shift_reg2.vhd new file mode 100644 index 0000000..c57121a --- /dev/null +++ b/polyphase_filter/poly_shift_reg2.vhd @@ -0,0 +1,79 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE work.POLY_FIR_PKG.ALL; + +ENTITY POLY_SHIFT_REG IS + PORT(i_clk : IN std_logic; + i_data : IN vect_adc_data_out; + o_data : OUT matrix3D_reg_data_out := (OTHERS => (OTHERS => (OTHERS => (OTHERS => '0')))) + ); +END POLY_SHIFT_REG; + +ARCHITECTURE Fill_Matrix OF POLY_SHIFT_REG IS + + TYPE vect_i_data_temp IS ARRAY (0 TO cst_nb_subfilters-1) OF smpl_adc_data_in; + TYPE matrix_i_data_temp IS ARRAY (0 TO 1) OF vect_i_data_temp; + SIGNAL data_matrix : matrix3D_reg_data_out := (OTHERS => (OTHERS => (OTHERS => (OTHERS => '0')))); + --SIGNAL data_temp : vect_reg_data := (OTHERS =>(OTHERS => '0')); + SIGNAL data_temp : matrix_reg_data := (OTHERS => (OTHERS => (OTHERS => '0'))); + --VARIABLE reg_i_data_temp : vect_i_data_temp := (OTHERS => (OTHERS => '0')); + +BEGIN + + + + -- purpose: fill a 3D matrix from a register. Each row is the input of the + -- input of a partial filter; each 2D matrix rows-columns is the input for a + -- subfilter + -- inputs: reg_i_data_temp, i_data + -- outputs: data_temp (3D matrix of std_logic_vectors) + PROCESS (i_clk) IS + VARIABLE subfilter_nb : natural := 0; + VARIABLE data_subfilter_nb : natural := 0; + VARIABLE reg_i_data_temp : matrix_i_data_temp; + BEGIN -- PROCESS + IF rising_edge(i_clk) THEN -- rising clock edge + + + + -- shifting the old samples towards data_temp(0) + FOR i IN 0 TO cst_nb_subfilters-1 LOOP + data_temp(i)(0 TO cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs-1) <= data_temp(i)(cst_nb_parallel_firs TO cst_nb_samples_shiftreg_temp_in-1); + END LOOP; -- i + + + + -- fill a temp 2D matrix for each subfilter (equivalent to filling a temp + -- vector for 1 filter) + parallel_fir_for : FOR parallel_fir_nb IN 0 TO cst_nb_parallel_firs-1 LOOP + + FOR i IN 0 TO cst_nb_subfilters-1 LOOP + reg_i_data_temp(1) := reg_i_data_temp(0); + END LOOP; + fill_previous_content : FOR data_nb IN cst_downsampling_factor TO cst_nb_subfilters-1 LOOP + data_temp(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= reg_i_data_temp(1)(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters)); + END LOOP fill_previous_content; -- data_nb + fill_data_temp : FOR data_nb IN 0 TO cst_downsampling_factor-1 LOOP -- fill data + data_temp(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= i_data(cst_downsampling_factor*parallel_fir_nb+data_nb); + reg_i_data_temp(0)(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters)) := i_data(cst_downsampling_factor*parallel_fir_nb+data_nb); + + END LOOP fill_data_temp; + END LOOP parallel_fir_for; -- parallel_fir_nb + + o_data <= data_matrix; + + END IF; + END PROCESS; + + + + -- purpose: wiring (filling the 3D out matrix) for each line, for each subfilter + third_dimension : FOR subfilter_nb IN 0 TO cst_nb_subfilters-1 GENERATE + second_dimension : FOR parallel_fir IN 0 TO cst_nb_parallel_firs-1 GENERATE + first_dimension : FOR data_nb IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE + data_matrix(subfilter_nb)(parallel_fir)(data_nb) <= data_temp(subfilter_nb)(data_nb+parallel_fir); + END GENERATE first_dimension; -- data_nb + END GENERATE second_dimension; -- parallel_fir + END GENERATE third_dimension; -- subfilter_nb + +END Fill_Matrix; diff --git a/polyphase_filter/tree_fir.vhd b/polyphase_filter/tree_fir.vhd new file mode 100644 index 0000000..0ab0ecb --- /dev/null +++ b/polyphase_filter/tree_fir.vhd @@ -0,0 +1,31 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE work.POLY_FIR_PKG.ALL; + +ENTITY TREE_FIR IS + PORT( i_clk : IN std_logic; + i_coeffs : IN vect_fir_coeffs_in; + i_data : IN matrix_reg_data_out; + o_data : OUT vect_fir_data_out := (OTHERS => (OTHERS => '0')) + ); +END TREE_FIR; + +ARCHITECTURE Simple_Fir OF TREE_FIR IS + + SIGNAL partial_fir_out : vect_fir_adder_data_out := (OTHERS => (OTHERS => '0')); + +BEGIN + + -- purpose: wiring: instanciation of each partial FIR to make 1 FIR + partial_fir_for : FOR i IN 0 TO cst_nb_parallel_firs-1 GENERATE + partial_fir_inst : ENTITY work.PARTIAL_FIR(Adder_Tree) + PORT MAP( i_clk => i_clk, + i_coeffs => i_coeffs, + i_data => i_data(i), + o_data => partial_fir_out(i) + ); + o_data(i)<= partial_fir_out(i)(cst_w_fir_adder_out-1 DOWNTO cst_w_fir_adder_out-cst_w_out); + END GENERATE partial_fir_for; + + +END Simple_Fir;