Transférer les fichiers vers 'polyphase_filter'

polyphase_filter/add_blk.vhd

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+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+ENTITY add_blk IS
+  GENERIC(w_out : IN natural);
+  PORT(i_clk   : IN  std_logic;
+       i_data1 : IN  smpl_adder_generic;
+       i_data2 : IN  smpl_adder_generic;
+       o_data  : OUT smpl_fir_adder_data_out := (OTHERS => '0')
+       );
+END add_blk;
+
+ARCHITECTURE add OF add_blk IS
+
+  SIGNAL smpl_stages_out : smpl_adder_generic := (OTHERS => '0');
+
+BEGIN  -- ARCHITECTURE add
+
+  -- purpose: creates the add process for the adding tree
+  -- type   : sequential
+  -- inputs : i_clk, i_data1, i_data2
+  -- outputs: o_data
+  adding_process : PROCESS (i_clk) IS
+  BEGIN  -- PROCESS adding_process
+    IF rising_edge(i_clk) THEN          -- rising clock edge
+      smpl_stages_out(w_out DOWNTO 0) <= std_logic_vector(unsigned(signed(i_data1(w_out-1)&i_data1(w_out-1 DOWNTO 0))+signed(i_data2(w_out-1)&i_data2(w_out-1 DOWNTO 0))));
+    END IF;
+  END PROCESS adding_process;
+
+  o_data <= smpl_stages_out;
+
+END ARCHITECTURE add;

polyphase_filter/mult_blk.vhd

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+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+ENTITY MULT_BLK IS
+  PORT(i_clk    : IN  std_logic;
+       i_data   : IN  vect_fir_data_in;
+       i_coeffs : IN  vect_fir_coeffs_in;
+       o_data   : OUT vect_mult_data_out := (OTHERS => (OTHERS =>'0'))
+       );
+END MULT_BLK;
+
+ARCHITECTURE Mult_Path OF MULT_BLK IS
+
+  SIGNAL data_mult_signed : vect_mult_data_out_signed := (OTHERS => (OTHERS => '0'));
+  SIGNAL coeffs_signed    : vect_mult_coeffs_signed := (OTHERS => (OTHERS => '0'));
+  SIGNAL data_signed      : vect_data_mult_in_signed := (OTHERS => (OTHERS => '0'));
+
+
+BEGIN
+
+  -- purpose: wiring: cast the i_data and i_coeffs into signed
+  cast : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
+    data_signed(i)   <= signed(i_data(i));
+    coeffs_signed(i) <= signed(i_coeffs(i));
+  END GENERATE cast;
+
+
+
+  -- purpose: calculate and send cast result to output
+  mult : PROCESS(i_clk)
+  BEGIN
+    IF rising_edge(i_clk) THEN
+      FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 LOOP
+        data_mult_signed(i) <= data_signed(i) * coeffs_signed(i);
+      END LOOP;
+    END IF;
+  END PROCESS;
+
+  o_data_wiring: FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
+    o_data(i) <= std_logic_vector(unsigned(data_mult_signed(i)));
+  END GENERATE o_data_wiring;
+
+END Mult_Path;

polyphase_filter/partial_fir.vhd

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+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+USE work.POLY_FIR_PKG.ALL;
+
+ENTITY PARTIAL_FIR IS
+  PORT(i_clk    : IN  std_logic;
+       i_coeffs : IN  vect_fir_coeffs_in;
+       i_data   : IN  vect_fir_data_in;
+       o_data   : OUT smpl_fir_adder_data_out := (OTHERS => '0')
+       );
+END PARTIAL_FIR;
+
+ARCHITECTURE Adder_Tree OF PARTIAL_FIR IS
+
+  SIGNAL matrix_adder_tree : matrix_adder_generic := (OTHERS => (OTHERS => (OTHERS => '0')));
+  --SIGNAL matrix_adder_tree_signed : matrix_adder_generic_signed := (OTHERS => (OTHERS => (OTHERS => '0')));
+  SIGNAL vect_i_coeffs     : vect_fir_coeffs_in := (OTHERS => (OTHERS => '0'));
+  SIGNAL mult_out          : vect_mult_data_out   := (OTHERS => (OTHERS => '0'));
+
+BEGIN
+
+
+
+  -- purpose: assign the filter in a decreasing order
+  in_assignment : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
+    vect_i_coeffs(i) <= i_coeffs(cst_nb_coeffs_subfilter_in-1-i);
+  END GENERATE in_assignment;
+
+
+
+  -- instanciation of MULT_BLK(Mult_Path), multiplying each element from i_data
+  -- with the correct coefficient in vect_i_coeffs
+  mult_inst : ENTITY work.MULT_BLK(Mult_Path)
+    PORT MAP(i_clk    => i_clk,
+             i_data   => i_data,
+             i_coeffs => vect_i_coeffs,
+             o_data   => mult_out
+             );
+
+
+
+  -- purpose: fill the input (which is the result of multiplication) of the addition tree matrix
+  -- inputs: mult_out
+  -- outputs:  matrix_adder_tree(0)
+  mult_out_wire : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
+    matrix_adder_tree(0)(i)(cst_w_mult_out-1 DOWNTO 0) <= mult_out(i)(cst_w_mult_out-1 DOWNTO 0);
+  END GENERATE mult_out_wire;
+
+
+
+  -- purpose: wiring: construct the adder tree. Construction:
+  --
+  -- 0-+--+----+->
+  -- 1/  /    /
+  -- 2-+/    /
+  -- 3/     /
+  -- 4-+--+/
+  -- 5/  /
+  -- 6-+/
+  -- 7/
+  --
+  -- inputs: matrix_adder_tree(0)
+  -- outputs: matrix_adder_tree(cst_log2_adder_stages)
+  stages_loop : FOR stage IN 1 TO cst_log2_adder_stages GENERATE
+    cell_loops : FOR cell IN 0 TO 2**(cst_log2_adder_stages-stage)-1 GENERATE
+
+       add_inst : ENTITY work.add_blk(add)
+        GENERIC MAP(w_out => cst_w_mult_out+stage-1)
+        PORT MAP(i_clk   => i_clk,
+                 i_data1 => matrix_adder_tree(stage-1)((2**(stage-1))*2*cell),
+                 i_data2 => matrix_adder_tree(stage-1)((2**(stage-1))*(2*cell+1)),
+                 o_data  => matrix_adder_tree(stage)((2**stage)*cell)
+                 );
+
+    END GENERATE cell_loops;
+  END GENERATE stages_loop;
+
+
+
+-- take the result when adder tree finished
+  o_data <= matrix_adder_tree(cst_log2_adder_stages)(0);
+
+END Adder_Tree;

polyphase_filter/poly_fir_blk.vhd

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+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+
+
+ENTITY poly_fir_blk IS
+
+  PORT (
+    i_clk    : IN  std_logic;
+    i_coeffs : IN  vect_polyfir_coeffs_in;
+    i_data   : IN  vect_adc_data_out;
+    o_data   : OUT matrix_fir_data_out := (OTHERS => (OTHERS => (OTHERS => '0')))
+    );
+
+END ENTITY poly_fir_blk;
+
+ARCHITECTURE polyphase OF poly_fir_blk IS
+
+  SIGNAL matrix3D_reg_out_simple_rif_in : matrix3D_reg_data_out := (OTHERS => (OTHERS => (OTHERS => (OTHERS => '0'))));
+  SIGNAL matrix_coeffs                  : matrix_fir_coeffs_in  := (OTHERS => (OTHERS => (OTHERS => '0')));
+  SIGNAL matrix_fir_out                 : matrix_fir_data_out   := (OTHERS => (OTHERS => (OTHERS => '0')));
+
+
+BEGIN  -- ARCHITECTURE polyphase
+
+
+
+  --purpose: fill the polyphase coefficients into a 2D matrix from the filter vector (1D)
+  fill_coeff : PROCESS(i_coeffs)        -- rearrange coeffs into a matrix
+    VARIABLE coeff_nb     : natural;
+    VARIABLE sf_coeff     : natural;
+    VARIABLE subfilter_nb : natural;
+  BEGIN
+    coeff_nb     := 0;
+    sf_coeff     := 0;
+    subfilter_nb := 0;
+    coeff_for_matrix : FOR coeff_nb IN 0 TO cst_nb_coeffs_filter_in-1 LOOP
+      matrix_coeffs(subfilter_nb)(sf_coeff) <= i_coeffs(coeff_nb);
+      subfilter_nb                          := subfilter_nb+1;
+      IF (subfilter_nb = cst_nb_subfilters) THEN
+        sf_coeff     := sf_coeff+1;
+        subfilter_nb := 0;
+      END IF;
+    END LOOP coeff_for_matrix;
+  END PROCESS fill_coeff;
+
+
+
+  -- instanciation of the shift-reg for polyphasd filter
+  shift_reg_inst : ENTITY work.POLY_SHIFT_REG(Fill_Matrix)
+    PORT MAP (i_clk  => i_clk,
+              i_data => i_data,
+              o_data => matrix3D_reg_out_simple_rif_in
+              );
+
+
+
+  wires_inst : ENTITY work.tree_firs(wires)
+    PORT MAP(
+      i_clk              => i_clk,
+      i_matrix3D_reg_out => matrix3D_reg_out_simple_rif_in,
+      i_coeffs           => matrix_coeffs,
+      o_data             => matrix_fir_out
+      );
+
+
+  o_data <= matrix_fir_out;
+
+END ARCHITECTURE polyphase;

polyphase_filter/poly_fir_blk__wires.vhd

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+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+
+
+ENTITY tree_firs IS
+
+  PORT (
+    i_clk : IN std_logic;
+    i_matrix3D_reg_out : IN  matrix3D_reg_data_out;
+    i_coeffs : IN matrix_fir_coeffs_in;
+    o_data : OUT matrix_fir_data_out := (OTHERS => (OTHERS => (OTHERS => '0')))
+    );
+
+END ENTITY tree_firs;
+
+ARCHITECTURE wires OF tree_firs IS
+
+
+BEGIN
+
+  -- instanciation of the cst_nb_subfilters subfilters
+  simple_fir_inst_loop : FOR i IN 0 TO cst_nb_subfilters-1 GENERATE
+    simple_fir_inst : ENTITY work.TREE_FIR(Simple_Fir)
+      PORT MAP(i_clk    => i_clk,
+               i_coeffs => i_coeffs(i),
+               i_data   => i_matrix3D_reg_out(i),
+               o_data   => o_data(i)
+               );
+  END GENERATE simple_fir_inst_loop;
+
+
+
+
+
+END ARCHITECTURE wires;