Browse Source

Supprimer 'partial_fir.vhd'

testing
Lilian RM 3 years ago
parent
commit
1499ad2dab
1 changed files with 0 additions and 85 deletions
  1. +0
    -85
      partial_fir.vhd

+ 0
- 85
partial_fir.vhd View File

@@ -1,85 +0,0 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.POLY_FIR_PKG.ALL;
ENTITY PARTIAL_FIR IS
PORT(i_clk : IN std_logic;
i_coeffs : IN vect_fir_coeffs_in;
i_data : IN vect_fir_data_in;
o_data : OUT smpl_fir_adder_data_out
);
END PARTIAL_FIR;
ARCHITECTURE Adder_Tree OF PARTIAL_FIR IS
SIGNAL matrix_adder_tree : matrix_adder_generic := (OTHERS => (OTHERS => (OTHERS => '0')));
SIGNAL matrix_adder_tree_signed : matrix_adder_generic_signed := (OTHERS => (OTHERS => (OTHERS => '0')));
SIGNAL vect_i_coeffs : vect_fir_coeffs_in;
SIGNAL mult_out : vect_mult_data_out := (OTHERS => (OTHERS => '0'));
BEGIN
-- purpose: assign the filter in a decreasing order
in_assignment : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
vect_i_coeffs(i) <= i_coeffs(cst_nb_coeffs_subfilter_in-1-i);
END GENERATE in_assignment;
-- instanciation of MULT_BLK(Mult_Path), multiplying each element from i_data
-- with the correct coefficient in vect_i_coeffs
mult_inst : ENTITY work.MULT_BLK(Mult_Path)
PORT MAP(i_clk => i_clk,
i_data => i_data,
i_coeffs => vect_i_coeffs,
o_data => mult_out(0 TO cst_nb_coeffs_subfilter_in-1)
);
-- purpose: fill the input (which is the result of multiplication) of the addition tree matrix
-- inputs: mult_out
-- outputs: matrix_adder_tree(0)
mult_out_wire : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
matrix_adder_tree(0)(i)(cst_w_mult_out-1 DOWNTO 0) <= mult_out(i)(cst_w_mult_out-1 DOWNTO 0);
END GENERATE mult_out_wire;
-- purpose: wiring: construct the adder tree. Construction:
--
-- 0-+--+----+->
-- 1/ / /
-- 2-+/ /
-- 3/ /
-- 4-+--+/
-- 5/ /
-- 6-+/
-- 7/
--
-- inputs: matrix_adder_tree(0)
-- outputs: matrix_adder_tree(cst_log2_adder_stages)
stages_loop : FOR stage IN 1 TO cst_log2_adder_stages GENERATE
cell_loops : FOR cell IN 0 TO 2**(cst_log2_adder_stages-stage)-1 GENERATE
matrix_adder_tree_signed(stage)((2**stage)*cell)(cst_w_mult_out+stage-1 DOWNTO 0) <= signed(matrix_adder_tree(stage-1)((2**stage)*cell)(cst_w_mult_out+stage-2)&matrix_adder_tree(stage-1)((2**stage)*cell)(cst_w_mult_out+stage-2 DOWNTO 0))+signed(matrix_adder_tree(stage-1)((2**(stage-1))*(2*cell+1))(cst_w_mult_out+stage-2)&matrix_adder_tree(stage-1)((2**(stage-1))*(2*cell+1))(cst_w_mult_out+stage-2 DOWNTO 0));
matrix_adder_tree(stage)((2**stage)*cell)(cst_w_mult_out+stage-1 DOWNTO 0) <= std_logic_vector(unsigned(matrix_adder_tree_signed(stage)((2**stage)*cell)(cst_w_mult_out+stage-1 DOWNTO 0)));
END GENERATE cell_loops;
END GENERATE stages_loop;
-- purpose: take the result when adder tree finished
adder_tree_process : PROCESS(i_clk)
BEGIN
IF(rising_edge(i_clk)) THEN
o_data <= matrix_adder_tree(cst_log2_adder_stages)(0);
END IF;
END PROCESS;
END Adder_Tree;

Loading…
Cancel
Save