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@@ -1,47 +0,0 @@ |
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE work.POLY_FIR_PKG.ALL;
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ENTITY MULT_BLK IS
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PORT(i_clk : IN std_logic;
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i_data : IN vect_fir_data_in;
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i_coeffs : IN vect_fir_coeffs_in;
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o_data : OUT vect_mult_data_out
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);
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END MULT_BLK;
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ARCHITECTURE Mult_Path OF MULT_BLK IS
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SIGNAL data_mult_signed : vect_mult_data_out_signed;
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SIGNAL coeffs_signed : vect_mult_coeffs_signed;
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SIGNAL data_signed : vect_data_mult_in_signed;
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BEGIN
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-- purpose: wiring: cast the i_data and i_coeffs into signed
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cast : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
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data_signed(i) <= signed(i_data(i));
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coeffs_signed(i) <= signed(i_coeffs(i));
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END GENERATE cast;
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-- purpose: calculte and send cast result to output
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mult : PROCESS(i_clk)
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BEGIN
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IF rising_edge(i_clk) THEN
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FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 LOOP
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data_mult_signed(i) <= data_signed(i) * coeffs_signed(i);
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END LOOP;
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ELSE
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data_mult_signed <= data_mult_signed;
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END IF;
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cast2 : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 LOOP
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o_data(i) <= std_logic_vector(unsigned(data_mult_signed(i)));
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END LOOP cast2;
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END PROCESS;
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END Mult_Path;
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