fir_vhdl/tree_fir.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.GENERAL_INCLUDES.ALL;

ENTITY TREE_FIR IS
  PORT(	i_clk 	: IN std_logic;
        i_coeffs	: IN vect_fir_coeffs_in;
        i_data 	: IN vect_adc_data_out;
        o_data	: OUT vect_fir_data_out
        );
END TREE_FIR;

ARCHITECTURE Shift_Reg_Fir OF TREE_FIR IS

  SIGNAL matrix_data_reg_out_mult_in : matrix_reg_data_out := (OTHERS => (OTHERS => (OTHERS => '0')));
  SIGNAL partial_fir_out : vect_fir_adder_data_out := (OTHERS => (OTHERS => '0'));

BEGIN

  shift_reg_inst : ENTITY work.SHIFT_REG(Fill_Matrix)
    GENERIC MAP(nb_samples_temp => cst_nb_samples_shiftreg_temp_in,
                nb_samples_line_matrix => cst_nb_coeffs_subfilter_in
                )
    PORT MAP(	i_clk 	=> i_clk,
                i_data 	=> i_data,
                o_data	=> matrix_data_reg_out_mult_in
                );
  
  partial_fir_for : FOR i IN 0 TO cst_nb_samples_adc_in-1 GENERATE
    partial_fir_inst : ENTITY work.PARTIAL_FIR(Adder_Tree)
      PORT MAP(	i_clk 	=> i_clk,
                i_coeffs	=> i_coeffs,
                i_data 	=> matrix_data_reg_out_mult_in(i),
                o_data	=> partial_fir_out(i)
		);
    o_data(i)<= partial_fir_out(i)(cst_w_fir_adder_out-1 DOWNTO cst_w_fir_adder_out-cst_w_out);
  END GENERATE partial_fir_for;


END Shift_Reg_Fir;