fir_vhdl/shift_reg.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.GENERAL_INCLUDES.ALL;

ENTITY SHIFT_REG IS
  GENERIC(nb_samples_temp : natural := cst_nb_samples_shiftreg_temp_in;
          nb_samples_line_matrix : natural := cst_nb_coeffs_subfilter_in
          );
  PORT(i_clk  : IN  std_logic;
       i_data : IN  vect_adc_data_out;
       o_data : OUT matrix_reg_data_out
       );
END SHIFT_REG;

ARCHITECTURE Fill_Matrix OF SHIFT_REG IS

  SIGNAL data_matrix   : matrix_reg_data_out;
  SIGNAL data_clk      : vect_reg_data;

BEGIN

  PROCESS(i_clk) IS
  BEGIN
    IF(rising_edge(i_clk)) THEN
      data_clk(0 TO nb_samples_temp-cst_nb_samples_adc_in-1)               <= data_clk(cst_nb_samples_adc_in TO nb_samples_temp-1);
      FOR i IN 0 TO cst_nb_samples_adc_in-1 LOOP
        data_clk(nb_samples_temp-cst_nb_samples_adc_in+i) <= i_data(i);
      END LOOP;  -- i
      FOR lines IN 0 TO cst_nb_samples_adc_in-1 LOOP
        -- the smaller line, the older samples
        FOR samples IN 0 TO nb_samples_line_matrix-1 LOOP
          data_matrix(lines)(samples) <= data_clk(lines+samples);
        END LOOP;
        
      END LOOP;
    ELSE
      data_clk <= data_clk;
    END IF;
    o_data <= data_matrix;
  END PROCESS;

END Fill_Matrix;