fir_vhdl/n_samples_partial_adder.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.GENERAL_INCLUDES.ALL;

ENTITY N_SAMPLES_PARTIAL_ADDER IS
  GENERIC( w_in : natural;
           nb_samples_out : natural
           );
  PORT(	i_clk 	: IN std_logic;
        i_data 	: IN ARRAY (0 TO 2*nb_samples_out-1) OF std_logic_vector(w_in-1 DOWNTO 0);
        o_data	: OUT ARRAY (0 TO nb_samples_out-1) OF std_logic_vector(w_in DOWNTO 0)
        );
END N_SAMPLES_PARTIAL_ADDER;

ARCHITECTURE Adder_Simple OF N_SAMPLES_PARTIAL_ADDER IS

  SIGNAL data1	: ARRAY (0 TO nb_samples_out) OF signed(w_in-1 DOWNTO 0);
  SIGNAL data2	: ARRAY (0 TO nb_samples_out) OF signed(w_in-1 DOWNTO 0);
  SIGNAL result	: ARRAY (0 TO nb_samples_out) OF signed(w_in DOWNTO 0);

BEGIN

  async_cast : FOR i IN 0 TO nb_samples_out-1 GENERATE
    data1(i) <= signed(i_data(2*i));
    data2(i) <= signed(i_data(2*i+1));
    o_data(i) <= std_logic_vector(result(i));
  END GENERATE async_cast;
  
  PROCESS(i_clk)
  BEGIN
    IF(rising_edge(i_clk)) THEN
      FOR i IN 0 TO nb_samples_out-1 LOOP
        result(i) <= data1(i) + data2(i);
      END LOOP;
    END IF;
  END PROCESS;

END Adder_Tree;