fir_vhdl/n_samples_adder.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.GENERAL_INCLUDES.ALL;

ENTITY N_SAMPLES_ADDER IS
  GENERIC( log2_nb_stages : natural
           );
  PORT(	i_clk 	: IN std_logic;
        i_data 	: IN ARRAY (0 TO 2*nb_samples_out) OF std_logic_vector(w_in-1 DOWNTO 0);
        o_data	: OUT std_logic_vector(w_in+cst_lo2_adder_stages-1 DOWNTO 0)
        );
END N_SAMPLES_ADDER;

ARCHITECTURE Adder_Simple OF N_SAMPLES_ADDER IS

  SIGNAL data1	: ARRAY (0 TO nb_samples_out) OF signed(w_in-1 DOWNTO 0);
  SIGNAL data2	: ARRAY (0 TO nb_samples_out) OF signed(w_in-1 DOWNTO 0);
  SIGNAL result	: ARRAY (0 TO nb_samples_out) OF signed(w_in DOWNTO 0);
  
  SIGNAL matrix_tree : matrix_adder_generic

BEGIN

  stages : FOR i IN 1 TO log2_nb_stages GENERATE
    ENTITY N_SAMPLES_partial_ADDER IS
      GENERIC( w_in => natural,
               nb_samples_out => natural
               )
        PORT(	i_clk 	=> i_clk,
                i_data 	=> IN ARRAY (0 TO 2*nb_samples_out) OF std_logic_vector(w_in-1 DOWNTO 0),
                o_data	=> OUT ARRAY (0 TO nb_samples_out) OF std_logic_vector(w_in DOWNTO 0)
                );
    END GENERATE stages;

    END Adder_Simple;