@@ -0,0 +1,6 @@ | |||||
library ieee; | |||||
USE ieee.std_logic_1164.all; | |||||
USE work.General_Includes.all; | |||||
package coeff is | |||||
CONSTANT fir_coeffs_generated : vect_fir_coeffs_in := (X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"ff",X"ff",X"ff",X"fe",X"fe",X"fe",X"fe",X"fe",X"fe",X"fe",X"fe",X"ff",X"ff"); | |||||
end package coeff; |
@@ -0,0 +1,131 @@ | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
USE ieee.numeric_std.ALL; | |||||
USE work.general_includes.ALL; | |||||
USE work.simu_pkg.ALL; | |||||
USE work.utils.ALL; | |||||
LIBRARY std; | |||||
USE std.textio.ALL; | |||||
USE work.coeff.ALL; | |||||
ENTITY simple_fir_tb IS | |||||
GENERIC ( | |||||
demi_periode : time := 5 ns; | |||||
-- duree de la demi periode des horloges | |||||
test_e : string := "D:\Stage\ALMA_OPFB\simu\simple_fir\tb_txts_files\input.txt"; | |||||
-- fichier test contenant les echantillons d'entree | |||||
test_s : string := "D:\Stage\ALMA_OPFB\simu\simple_fir\tb_txts_files\output.txt" | |||||
-- fichier contenant les echantillons de sortie | |||||
--fir_addr : std_logic_vector(band5a_w_fc-1 DOWNTO 0) := std_logic_vector(unsigned(band5a_fc_index, band5a_w_fc)) | |||||
-- coef de décimation | |||||
); | |||||
END simple_fir_tb; | |||||
ARCHITECTURE beh OF simple_fir_tb IS | |||||
FILE fichier_e : text IS IN test_e; | |||||
FILE fichier_s : text IS IN test_s; | |||||
--FILE fichier_c : text IS IN test_c; | |||||
SIGNAL initialisation : std_logic; | |||||
SIGNAL h : std_logic; | |||||
SIGNAL entree_fir : vect_adc_data_out := (OTHERS => (OTHERS => '0')); | |||||
SIGNAL sortie_fir : vect_fir_data_out := (OTHERS => (OTHERS => '0')); | |||||
SIGNAL sortie_fir_sim : vect_fir_data_out := (OTHERS => (OTHERS => '0')); | |||||
--SIGNAL coeffs_fir : vect_fir_coeffs_in := ; | |||||
BEGIN -- ARCHITECTURE beh | |||||
module_simu : ENTITY work.Tree_Fir(Shift_Reg_Fir) | |||||
PORT MAP (h, fir_coeffs_generated, entree_fir, sortie_fir_sim); | |||||
horloge_entree : horloge(h, demi_periode, demi_periode); | |||||
source : PROCESS | |||||
CONSTANT header : natural := 1; -- nombre de ligne d'en tête | |||||
CONSTANT nbr_ech : natural := 249870; -- nombre d'echantillons d'entree dans le fichier test | |||||
CONSTANT mots_ligne : natural := cst_nb_samples_adc_in; -- nombre de mots par ligne dans le ficher | |||||
VARIABLE nbr_ligne : natural := 24987; --2750; --15625; -- nombre de lignes restant à lire dans le fichier | |||||
VARIABLE i : natural := 1; | |||||
VARIABLE donnee : integer; | |||||
VARIABLE tempo : natural := 0; | |||||
VARIABLE ligne : line; | |||||
VARIABLE head : boolean := false; | |||||
BEGIN -- PROCESS source | |||||
WAIT UNTIL falling_edge(h); | |||||
IF head = true THEN | |||||
head := false; | |||||
FOR i IN 0 TO header-1 LOOP | |||||
readline(fichier_e, ligne); | |||||
END LOOP; | |||||
END IF; | |||||
IF tempo > 0 THEN -- temps de synchro | |||||
tempo := tempo -1; | |||||
ELSIF nbr_ligne > 0 THEN | |||||
readline(fichier_e, ligne); | |||||
nbr_ligne := nbr_ligne-1; | |||||
FOR k IN 0 TO mots_ligne -1 LOOP | |||||
read(ligne, donnee); | |||||
entree_fir(k) <= std_logic_vector(to_signed(donnee, cst_w_in)); | |||||
END LOOP; -- k | |||||
END IF; | |||||
END PROCESS source; | |||||
test : PROCESS | |||||
CONSTANT header : natural := 1; -- nombre de ligne d'en tête | |||||
CONSTANT nbr_ech : natural := 249870;--nombre d'echantillons d'entree dans le fichier test | |||||
CONSTANT mots_ligne : natural := 10; -- nombre de mots par ligne dans le ficher | |||||
VARIABLE nbr_ligne : natural := 24987; -- nombre de lignes restant à lire dans le fichier | |||||
VARIABLE i : natural; | |||||
VARIABLE donnee : donnee_sortie; | |||||
VARIABLE ligne : line; | |||||
VARIABLE tempo : natural := 6; | |||||
VARIABLE sortie : integer; | |||||
VARIABLE head : boolean := false; | |||||
BEGIN -- PROCESS test | |||||
WAIT UNTIL falling_edge(h); | |||||
IF tempo > 0 THEN -- temps de synchro | |||||
tempo := tempo -1; | |||||
ASSERT false REPORT "Attente_2 ... " SEVERITY note; | |||||
ELSIF nbr_ligne > 0 THEN | |||||
readline(fichier_s, ligne); | |||||
nbr_ligne := nbr_ligne-1; | |||||
FOR k IN 0 TO mots_ligne -1 LOOP | |||||
read(ligne, donnee(k)); | |||||
sortie := to_integer(signed(sortie_fir_sim(k))); | |||||
sortie_fir(k) <= std_logic_vector(to_signed(donnee(k), cst_w_out)); | |||||
ASSERT sortie = donnee(k) REPORT "Valeur fir FAUSSE" | |||||
SEVERITY error; | |||||
--ASSERT sortie /= donnee(k) REPORT "OK" | |||||
-- SEVERITY note; | |||||
END LOOP; -- k | |||||
END IF; | |||||
END PROCESS test; | |||||
END ARCHITECTURE beh; |
@@ -0,0 +1,263 @@ | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
USE ieee.numeric_std.ALL; | |||||
USE ieee.std_logic_unsigned.ALL; | |||||
USE ieee.std_logic_signed.ALL; | |||||
PACKAGE GENERAL_INCLUDES IS | |||||
FUNCTION log2_sup_integer (number : natural) RETURN natural; | |||||
FUNCTION log2_inf_integer (number : natural) RETURN natural; | |||||
-- -- CONSTANTS -- -- | |||||
-- ADC | |||||
CONSTANT cst_w_in : natural := 6; -- ADC in bitwidth | |||||
CONSTANT cst_w_out : natural := 19; | |||||
CONSTANT cst_nb_samples_adc_in : natural := 10; -- ADC in nb samples | |||||
-- FILTER | |||||
--coefficients | |||||
CONSTANT cst_w_coeff : natural := 8; -- coeffs bitwidth | |||||
CONSTANT cst_nb_coeffs_filter_in : natural := 20*10; | |||||
CONSTANT cst_log2_sup_nb_coeffs_subfilter_in: natural:= 5; | |||||
-- FIR | |||||
-- POLYPHASE FILTER | |||||
CONSTANT cst_nb_subfilters : natural := 10; | |||||
-- -- CALCULATIONS -- -- | |||||
-- SHIFT REG | |||||
CONSTANT cst_nb_coeffs_subfilter_in : natural := cst_nb_coeffs_filter_in/cst_nb_subfilters; | |||||
CONSTANT cst_nb_samples_shiftreg_temp_in : natural := cst_nb_coeffs_subfilter_in + cst_nb_samples_adc_in; | |||||
-- mult | |||||
CONSTANT cst_w_mult_out : natural := cst_w_coeff+cst_w_in; | |||||
-- adder | |||||
CONSTANT cst_log2_adder_stages : natural := cst_log2_sup_nb_coeffs_subfilter_in; | |||||
-- fir | |||||
CONSTANT cst_w_fir_adder_out : natural := cst_w_mult_out+cst_log2_adder_stages; | |||||
-- TYPES | |||||
-- ADC | |||||
SUBTYPE smpl_adc_data_in IS std_logic_vector(cst_w_in-1 DOWNTO 0); | |||||
SUBTYPE smpl_fir_data_out IS std_logic_vector(cst_w_out-1 DOWNTO 0); | |||||
-- SHIFT REG | |||||
TYPE vect_adc_data_out IS ARRAY (0 TO cst_nb_samples_adc_in-1) OF smpl_adc_data_in; | |||||
TYPE vect_fir_data_in IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_adc_data_in; | |||||
TYPE vect_reg_data IS ARRAY(0 TO cst_nb_samples_shiftreg_temp_in-1) OF smpl_adc_data_in; | |||||
TYPE matrix_reg_data_out IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF vect_fir_data_in; | |||||
-- FILTER | |||||
SUBTYPE smpl_coeff IS std_logic_vector(cst_w_coeff-1 DOWNTO 0); | |||||
-- mult | |||||
SUBTYPE smpl_mult_data_out IS std_logic_vector(cst_w_mult_out-1 DOWNTO 0); | |||||
SUBTYPE smpl_mult_data_out_signed IS signed(cst_w_mult_out-1 DOWNTO 0); | |||||
SUBTYPE smpl_coeffs_signed IS signed(cst_w_coeff-1 DOWNTO 0); | |||||
SUBTYPE smpl_mult_data_in_signed IS signed(cst_w_in-1 DOWNTO 0); | |||||
TYPE vect_data_mult_in_signed IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_mult_data_in_signed; | |||||
TYPE vect_fir_coeffs_in IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_coeff ; | |||||
TYPE vect_mult_coeffs_signed IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_coeffs_signed; | |||||
TYPE vect_mult_data_out IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_mult_data_out; | |||||
TYPE vect_mult_data_out_signed IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_mult_data_out_signed; | |||||
-- adder | |||||
TYPE vect_adder_generic IS ARRAY(0 TO 2**(cst_log2_adder_stages)-1) OF std_logic_vector(cst_w_fir_adder_out-1 DOWNTO 0); | |||||
TYPE vect_adder_generic_signed IS ARRAY(0 TO 2**(cst_log2_adder_stages)-1) OF signed(cst_w_fir_adder_out-1 DOWNTO 0); | |||||
TYPE matrix_adder_generic IS ARRAY(0 TO cst_log2_adder_stages) OF vect_adder_generic; | |||||
TYPE matrix_adder_generic_signed IS ARRAY(0 TO cst_log2_adder_stages) OF vect_adder_generic_signed; | |||||
-- fir | |||||
SUBTYPE smpl_fir_adder_data_out IS std_logic_vector(cst_w_fir_adder_out-1 DOWNTO 0); | |||||
TYPE vect_fir_adder_data_out IS ARRAY (0 TO cst_nb_samples_adc_in-1) OF smpl_fir_adder_data_out; | |||||
TYPE vect_fir_data_out IS array(0 TO cst_nb_samples_adc_in-1) OF smpl_fir_data_out; | |||||
-- POLYPHASE FILTER | |||||
-- TYPE matrix_coeffs_polyphase_filter IS array(0 to cst_nb_subfilters) OF vect_mult_coeffs; | |||||
-- ---- CONSTANTS ---- | |||||
-- | |||||
-- -- data | |||||
-- CONSTANT w_x : natural := 6; -- input samples bitwidth | |||||
-- CONSTANT w_y : natural := 6; -- output data bitwidth | |||||
-- | |||||
-- | |||||
-- -- filter | |||||
-- CONSTANT filer_nb_coeffs : natural := 1000; -- total nb coefficients | |||||
-- CONSTANT filter_nb_channels : natural := 20; -- nb subfilters | |||||
-- CONSTANT w_coeffs : natural := 8; -- | |||||
-- | |||||
-- -- signal processing properties | |||||
-- CONSTANT downsampling_factor : natural := 8; | |||||
-- | |||||
-- | |||||
-- | |||||
-- ---- CALCULATIONS ---- | |||||
-- | |||||
-- | |||||
-- VARIABLE subfilter_coeffs_nb_temp : natural := filer_nb_coeffs/filter_nb_channels; | |||||
-- if(2**(log2_sup_integer(subfilter_coeffs_nb_temp)) != subfilter_coeffs_nb_temp) then -- if not power of 2 | |||||
-- CONSTANT subfilter_coeffs_nb : natural := 2**(log2_sup_integer(subfilter_coeffs_nb_temp); | |||||
-- else | |||||
-- CONSTANT subfilter_coeffs_nb : natural := subfilter_coeffs_nb_temp; | |||||
-- end if; | |||||
-- | |||||
-- CONSTANT log_subfilter_coeffs_nb : natural := log2_sup_integer(subfilter_coeffs_nb); | |||||
-- | |||||
-- -- FIR | |||||
-- --multplier | |||||
-- CONSTANT data_mult_in_w : natural := w_x; | |||||
-- CONSTANT data_mult_out_w : natural := w_x+w_coeffs+1; | |||||
-- --adder | |||||
-- CONSTANT data_add_in_w : natural := data_mult_out_w; | |||||
-- CONSTANT data_P_G_stages : natural := natural(conv_std_logic_vector(data_add_in_w)'LENGTH) -- ca marche? | |||||
-- CONSTANT data_add_out_w : natural := data_add_in_w+log_subfilter_coeffs_nb; | |||||
-- | |||||
-- | |||||
-- ---- TYPES ---- | |||||
-- | |||||
-- -- filter coeffs | |||||
-- TYPE coeff IS std_logic_vector(w_coeffs-1 downto 0); | |||||
-- TYPE coeff_signed IS signed(w_coeffs-1 downto 0); | |||||
-- TYPE subfilter_coefficients IS array(0 to subfilter_coeffs_nb-1) OF coeff; | |||||
-- TYPE polyphase_filter_matrix IS array(0 to filter_nb_channels-1) OF subfilter_coefficients; | |||||
-- | |||||
-- -- polyphase fill | |||||
-- polyphase_filter_matrix(others =>(others => 0); -- init; | |||||
-- | |||||
-- for subfilter_nth_coeff in (0 to subfilter_coeffs_nb-1) loop -- fill subfilters | |||||
-- for lines in (0 to filter_nb_channels-1) loop | |||||
-- polyphase_filter_matrix(lines => (subfilter_nth_coeff => filter(lines*filter_nb_channels+subfilter_nth_coeff)); | |||||
-- end loop; | |||||
-- end loop; | |||||
-- | |||||
-- -- FIR | |||||
-- TYPE fir_data_in IS std_logic_vector(w_x-1 downto 0); | |||||
-- TYPE fir_data_out IS std_logic_vector(w_x+log_subfilter_coeffs_nb-1 downto 0); | |||||
-- --reg | |||||
-- TYPE data_reg_in IS data_in; | |||||
-- --multiplier | |||||
-- TYPE data_mult_in IS std_logic_vector(data_mult_in_w-1 downto 0); | |||||
-- TYPE data_mult_in_signed IS signed(data_mult_in_w-1 downto 0); | |||||
-- TYPE data_mult_out IS std_logic_vector(data_mult_out_w-1 downto 0); | |||||
-- TYPE data_mult_out_signed IS signed(data_mult_out_w-1 downto 0); | |||||
-- --adder | |||||
-- TYPE data_add_in IS data_mult_out; | |||||
-- TYPE data_add_out IS STD_LOGIC_VECTOR(data_add_out_w-1 downto 0); | |||||
-- --tree | |||||
-- TYPE mult_add_stage_array IS array(0 to subfilter_coeffs_nb-1) OF data_add_out; | |||||
-- TYPE mult_add_tree_matrix IS array(0 to log_subfilter_coeffs_nb) OF mult_add_stage_array; | |||||
-- --DFT | |||||
-- TYPE input_DFT_data IS data_add_out; | |||||
-- TYPE output_DFT_data IS | |||||
-- | |||||
-- --TYPE step_nb_channels IS array (0 to filter_nb_channels-1) of signed (w_x-1 downto 0); | |||||
-- --TYPE filter_coeffs IS array (0 to filer_nb_coeffs-1) of signed (w_x-1 downto 0); | |||||
-- --TYPE type_data_fir IS signed(w_x-1 downto 0); | |||||
-- --TYPE type_coeff_fir IS signed | |||||
END; | |||||
PACKAGE BODY GENERAL_INCLUDES IS | |||||
--functions | |||||
FUNCTION log2_sup_integer (number : natural) RETURN natural IS | |||||
VARIABLE result : natural; | |||||
BEGIN | |||||
IF(number <= 1) THEN | |||||
result := 0; | |||||
ELSIF(number = 2) THEN | |||||
result := 1; | |||||
ELSIF(number > 2 AND number <= 4) THEN | |||||
result := 2; | |||||
ELSIF(number > 4 AND number <= 8) THEN | |||||
result := 3; | |||||
ELSIF(number > 8 AND number <= 16) THEN | |||||
result := 4; | |||||
ELSIF(number > 16 AND number <= 32) THEN | |||||
result := 5; | |||||
ELSIF(number > 32 AND number <= 64) THEN | |||||
result := 6; | |||||
ELSIF(number > 64 AND number <= 128) THEN | |||||
result := 7; | |||||
ELSIF(number > 128 AND number <= 256) THEN | |||||
result := 8; | |||||
ELSIF(number > 256 AND number <= 512) THEN | |||||
result := 9; | |||||
ELSIF(number > 512 AND number <= 1024) THEN | |||||
result := 10; | |||||
ELSIF(number > 1024 AND number <= 2048) THEN | |||||
result := 11; | |||||
ELSIF(number > 2048 AND number <= 4096) THEN | |||||
result := 12; | |||||
ELSIF(number > 4096 AND number <= 8192) THEN | |||||
result := 13; | |||||
ELSIF(number > 8192 AND number <= 16384) THEN | |||||
result := 14; | |||||
ELSIF(number > 16384 AND number <= 32768) THEN | |||||
result := 15; | |||||
END IF; | |||||
RETURN result; | |||||
END FUNCTION; | |||||
FUNCTION log2_inf_integer (number : natural) RETURN natural IS | |||||
VARIABLE result : natural; | |||||
BEGIN | |||||
IF(number < 2) THEN | |||||
result := 0; | |||||
ELSIF(number >= 2 AND number < 4) THEN | |||||
result := 1; | |||||
ELSIF(number >= 4 AND number < 8) THEN | |||||
result := 2; | |||||
ELSIF(number >= 8 AND number < 16) THEN | |||||
result := 3; | |||||
ELSIF(number >= 16 AND number < 32) THEN | |||||
result := 4; | |||||
ELSIF(number >= 32 AND number < 64) THEN | |||||
result := 5; | |||||
ELSIF(number >= 64 AND number < 128) THEN | |||||
result := 6; | |||||
ELSIF(number >= 128 AND number < 256) THEN | |||||
result := 7; | |||||
ELSIF(number >= 256 AND number < 512) THEN | |||||
result := 8; | |||||
ELSIF(number >= 512 AND number < 1024) THEN | |||||
result := 9; | |||||
ELSIF(number >= 1024 AND number < 2048) THEN | |||||
result := 10; | |||||
ELSIF(number >= 2048 AND number < 4096) THEN | |||||
Result := 11; | |||||
ELSIF(Number >= 4096 AND number < 8192) THEN | |||||
result := 12; | |||||
ELSIF(number >= 8192 AND number < 16384) THEN | |||||
result := 13; | |||||
ELSIF(number >= 16384 AND number < 32768) THEN | |||||
result := 14; | |||||
END IF; | |||||
RETURN result; | |||||
END FUNCTION; | |||||
END PACKAGE BODY; |
@@ -0,0 +1,43 @@ | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
USE ieee.numeric_std.ALL; | |||||
USE work.general_includes.ALL; | |||||
ENTITY MULT_BLK IS | |||||
PORT(i_clk : IN std_logic; | |||||
i_data : IN vect_fir_data_in; | |||||
i_coeffs : IN vect_fir_coeffs_in; | |||||
o_data : OUT vect_mult_data_out | |||||
); | |||||
END MULT_BLK; | |||||
ARCHITECTURE Mult_Path OF MULT_BLK IS | |||||
SIGNAL data_mult_signed : vect_mult_data_out_signed; | |||||
SIGNAL coeffs_signed : vect_mult_coeffs_signed; | |||||
SIGNAL data_signed : vect_data_mult_in_signed; | |||||
BEGIN | |||||
cast : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE | |||||
data_signed(i) <= signed(i_data(i)); | |||||
coeffs_signed(i) <= signed(i_coeffs(i)); | |||||
END GENERATE cast; | |||||
mult : PROCESS(i_clk) | |||||
BEGIN | |||||
IF rising_edge(i_clk) THEN | |||||
FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 LOOP | |||||
data_mult_signed(i) <= data_signed(i) * coeffs_signed(i); | |||||
END LOOP; | |||||
ELSE | |||||
data_mult_signed <= data_mult_signed; | |||||
END IF; | |||||
cast2: FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 LOOP | |||||
o_data(i) <= std_logic_vector(unsigned(data_mult_signed(i))); | |||||
END LOOP cast2; | |||||
END PROCESS; | |||||
END Mult_Path; |
@@ -0,0 +1,35 @@ | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
USE work.GENERAL_INCLUDES.ALL; | |||||
ENTITY N_SAMPLES_ADDER IS | |||||
GENERIC( log2_nb_stages : natural | |||||
); | |||||
PORT( i_clk : IN std_logic; | |||||
i_data : IN ARRAY (0 TO 2*nb_samples_out) OF std_logic_vector(w_in-1 DOWNTO 0); | |||||
o_data : OUT std_logic_vector(w_in+cst_lo2_adder_stages-1 DOWNTO 0) | |||||
); | |||||
END N_SAMPLES_ADDER; | |||||
ARCHITECTURE Adder_Simple OF N_SAMPLES_ADDER IS | |||||
SIGNAL data1 : ARRAY (0 TO nb_samples_out) OF signed(w_in-1 DOWNTO 0); | |||||
SIGNAL data2 : ARRAY (0 TO nb_samples_out) OF signed(w_in-1 DOWNTO 0); | |||||
SIGNAL result : ARRAY (0 TO nb_samples_out) OF signed(w_in DOWNTO 0); | |||||
SIGNAL matrix_tree : matrix_adder_generic | |||||
BEGIN | |||||
stages : FOR i IN 1 TO log2_nb_stages GENERATE | |||||
ENTITY N_SAMPLES_partial_ADDER IS | |||||
GENERIC( w_in => natural, | |||||
nb_samples_out => natural | |||||
) | |||||
PORT( i_clk => i_clk, | |||||
i_data => IN ARRAY (0 TO 2*nb_samples_out) OF std_logic_vector(w_in-1 DOWNTO 0), | |||||
o_data => OUT ARRAY (0 TO nb_samples_out) OF std_logic_vector(w_in DOWNTO 0) | |||||
); | |||||
END GENERATE stages; | |||||
END Adder_Simple; |
@@ -0,0 +1,38 @@ | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
USE work.GENERAL_INCLUDES.ALL; | |||||
ENTITY N_SAMPLES_PARTIAL_ADDER IS | |||||
GENERIC( w_in : natural; | |||||
nb_samples_out : natural | |||||
); | |||||
PORT( i_clk : IN std_logic; | |||||
i_data : IN ARRAY (0 TO 2*nb_samples_out-1) OF std_logic_vector(w_in-1 DOWNTO 0); | |||||
o_data : OUT ARRAY (0 TO nb_samples_out-1) OF std_logic_vector(w_in DOWNTO 0) | |||||
); | |||||
END N_SAMPLES_PARTIAL_ADDER; | |||||
ARCHITECTURE Adder_Simple OF N_SAMPLES_PARTIAL_ADDER IS | |||||
SIGNAL data1 : ARRAY (0 TO nb_samples_out) OF signed(w_in-1 DOWNTO 0); | |||||
SIGNAL data2 : ARRAY (0 TO nb_samples_out) OF signed(w_in-1 DOWNTO 0); | |||||
SIGNAL result : ARRAY (0 TO nb_samples_out) OF signed(w_in DOWNTO 0); | |||||
BEGIN | |||||
async_cast : FOR i IN 0 TO nb_samples_out-1 GENERATE | |||||
data1(i) <= signed(i_data(2*i)); | |||||
data2(i) <= signed(i_data(2*i+1)); | |||||
o_data(i) <= std_logic_vector(result(i)); | |||||
END GENERATE async_cast; | |||||
PROCESS(i_clk) | |||||
BEGIN | |||||
IF(rising_edge(i_clk)) THEN | |||||
FOR i IN 0 TO nb_samples_out-1 LOOP | |||||
result(i) <= data1(i) + data2(i); | |||||
END LOOP; | |||||
END IF; | |||||
END PROCESS; | |||||
END Adder_Tree; |
@@ -0,0 +1,57 @@ | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
USE ieee.numeric_std.ALL; | |||||
USE work.GENERAL_INCLUDES.ALL; | |||||
ENTITY PARTIAL_FIR IS | |||||
PORT( i_clk : IN std_logic; | |||||
i_coeffs : IN vect_fir_coeffs_in; | |||||
i_data : IN vect_fir_data_in; | |||||
o_data : OUT smpl_fir_adder_data_out | |||||
); | |||||
END PARTIAL_FIR; | |||||
ARCHITECTURE Adder_Tree OF PARTIAL_FIR IS | |||||
SIGNAL matrix_adder_tree : matrix_adder_generic := (OTHERS => (OTHERS => (OTHERS => '0'))); | |||||
SIGNAL matrix_adder_tree_signed : matrix_adder_generic_signed := (OTHERS => (OTHERS => (OTHERS => '0'))); | |||||
SIGNAL vect_i_coeffs : vect_fir_coeffs_in; | |||||
SIGNAL mult_out : vect_mult_data_out := (OTHERS => (OTHERS => '0')); | |||||
BEGIN | |||||
in_assignment : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE | |||||
vect_i_coeffs(i) <= i_coeffs(cst_nb_coeffs_subfilter_in-1-i); | |||||
END GENERATE in_assignment; | |||||
mult_inst : ENTITY work.MULT_BLK(Mult_Path) | |||||
PORT MAP( i_clk => i_clk, | |||||
i_data => i_data, | |||||
i_coeffs => vect_i_coeffs, | |||||
o_data => mult_out(0 TO cst_nb_coeffs_subfilter_in-1) | |||||
); | |||||
mult_out_wire : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE | |||||
matrix_adder_tree(0)(i)(cst_w_mult_out-1 DOWNTO 0) <= mult_out(i)(cst_w_mult_out-1 DOWNTO 0); | |||||
END GENERATE mult_out_wire; | |||||
stages_loop : FOR stage IN 1 TO cst_log2_adder_stages GENERATE | |||||
cell_loops : FOR cell IN 0 TO 2**(cst_log2_adder_stages-stage)-1 GENERATE | |||||
matrix_adder_tree_signed(stage)((2**stage)*cell)(cst_w_mult_out+stage-1 DOWNTO 0) <= signed(matrix_adder_tree(stage-1)((2**stage)*cell)(cst_w_mult_out+stage-2)&matrix_adder_tree(stage-1)((2**stage)*cell)(cst_w_mult_out+stage-2 DOWNTO 0))+signed(matrix_adder_tree(stage-1)((2**(stage-1))*(2*cell+1))(cst_w_mult_out+stage-2)&matrix_adder_tree(stage-1)((2**(stage-1))*(2*cell+1))(cst_w_mult_out+stage-2 DOWNTO 0)); | |||||
matrix_adder_tree(stage)((2**stage)*cell)(cst_w_mult_out+stage-1 DOWNTO 0) <= std_logic_vector(unsigned(matrix_adder_tree_signed(stage)((2**stage)*cell)(cst_w_mult_out+stage-1 DOWNTO 0))); | |||||
END GENERATE cell_loops; | |||||
END GENERATE stages_loop; | |||||
adder_tree_process : PROCESS(i_clk) | |||||
BEGIN | |||||
IF(rising_edge(i_clk)) THEN | |||||
o_data <= matrix_adder_tree(cst_log2_adder_stages)(0); | |||||
END IF; | |||||
END PROCESS; | |||||
END Adder_Tree; |
@@ -0,0 +1,42 @@ | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
USE work.GENERAL_INCLUDES.ALL; | |||||
ENTITY SHIFT_REG IS | |||||
GENERIC(nb_samples_temp : natural := cst_nb_samples_shiftreg_temp_in; | |||||
nb_samples_line_matrix : natural := cst_nb_coeffs_subfilter_in | |||||
); | |||||
PORT(i_clk : IN std_logic; | |||||
i_data : IN vect_adc_data_out; | |||||
o_data : OUT matrix_reg_data_out | |||||
); | |||||
END SHIFT_REG; | |||||
ARCHITECTURE Fill_Matrix OF SHIFT_REG IS | |||||
SIGNAL data_matrix : matrix_reg_data_out; | |||||
SIGNAL data_clk : vect_reg_data; | |||||
BEGIN | |||||
PROCESS(i_clk) IS | |||||
BEGIN | |||||
IF(rising_edge(i_clk)) THEN | |||||
data_clk(0 TO nb_samples_temp-cst_nb_samples_adc_in-1) <= data_clk(cst_nb_samples_adc_in TO nb_samples_temp-1); | |||||
FOR i IN 0 TO cst_nb_samples_adc_in-1 LOOP | |||||
data_clk(nb_samples_temp-cst_nb_samples_adc_in+i) <= i_data(i); | |||||
END LOOP; -- i | |||||
FOR lines IN 0 TO cst_nb_samples_adc_in-1 LOOP | |||||
-- the smaller line, the older samples | |||||
FOR samples IN 0 TO nb_samples_line_matrix-1 LOOP | |||||
data_matrix(lines)(samples) <= data_clk(lines+samples); | |||||
END LOOP; | |||||
END LOOP; | |||||
ELSE | |||||
data_clk <= data_clk; | |||||
END IF; | |||||
o_data <= data_matrix; | |||||
END PROCESS; | |||||
END Fill_Matrix; |
@@ -0,0 +1,13 @@ | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
USE ieee.numeric_std.ALL; | |||||
USE work.general_includes.ALL; | |||||
PACKAGE simu_pkg IS | |||||
TYPE donnee_sortie IS ARRAY (0 TO cst_nb_samples_adc_in-1) OF integer; | |||||
CONSTANT w_x_simu : natural := 4; | |||||
END; |
@@ -0,0 +1,40 @@ | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
USE work.GENERAL_INCLUDES.ALL; | |||||
ENTITY TREE_FIR IS | |||||
PORT( i_clk : IN std_logic; | |||||
i_coeffs : IN vect_fir_coeffs_in; | |||||
i_data : IN vect_adc_data_out; | |||||
o_data : OUT vect_fir_data_out | |||||
); | |||||
END TREE_FIR; | |||||
ARCHITECTURE Shift_Reg_Fir OF TREE_FIR IS | |||||
SIGNAL matrix_data_reg_out_mult_in : matrix_reg_data_out := (OTHERS => (OTHERS => (OTHERS => '0'))); | |||||
SIGNAL partial_fir_out : vect_fir_adder_data_out := (OTHERS => (OTHERS => '0')); | |||||
BEGIN | |||||
shift_reg_inst : ENTITY work.SHIFT_REG(Fill_Matrix) | |||||
GENERIC MAP(nb_samples_temp => cst_nb_samples_shiftreg_temp_in, | |||||
nb_samples_line_matrix => cst_nb_coeffs_subfilter_in | |||||
) | |||||
PORT MAP( i_clk => i_clk, | |||||
i_data => i_data, | |||||
o_data => matrix_data_reg_out_mult_in | |||||
); | |||||
partial_fir_for : FOR i IN 0 TO cst_nb_samples_adc_in-1 GENERATE | |||||
partial_fir_inst : ENTITY work.PARTIAL_FIR(Adder_Tree) | |||||
PORT MAP( i_clk => i_clk, | |||||
i_coeffs => i_coeffs, | |||||
i_data => matrix_data_reg_out_mult_in(i), | |||||
o_data => partial_fir_out(i) | |||||
); | |||||
o_data(i)<= partial_fir_out(i)(cst_w_fir_adder_out-1 DOWNTO cst_w_fir_adder_out-cst_w_out); | |||||
END GENERATE partial_fir_for; | |||||
END Shift_Reg_Fir; |
@@ -0,0 +1,33 @@ | |||||
-- *********************** Divers fonction utiles *************************** | |||||
LIBRARY ieee; | |||||
USE ieee.std_logic_1164.ALL; | |||||
PACKAGE utils IS | |||||
PROCEDURE horloge ( SIGNAL h: OUT std_logic; th, tb : time); | |||||
PROCEDURE horloge_retard ( SIGNAL h : OUT std_logic; periode : time ; | |||||
retard : time); | |||||
END utils; | |||||
--------------------------------------------------- | |||||
PACKAGE BODY utils IS | |||||
PROCEDURE horloge ( SIGNAL h : OUT std_logic; th, tb : time) IS | |||||
BEGIN | |||||
LOOP | |||||
h <= '0', '1' AFTER tb; | |||||
WAIT FOR tb + th ; | |||||
END LOOP; | |||||
END; | |||||
PROCEDURE horloge_retard ( SIGNAL h : OUT std_logic; periode : time ; | |||||
retard : time) IS | |||||
BEGIN | |||||
h <= '0'; | |||||
WAIT FOR retard; | |||||
LOOP | |||||
h <= '1' , '0' AFTER periode/2 ; | |||||
WAIT FOR periode; | |||||
END LOOP; | |||||
END; | |||||
END utils; |