Simulation files of Polyphase Filter in VHDL for FPGA.
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  1. LIBRARY ieee;
  2. USE ieee.std_logic_1164.ALL;
  3. USE ieee.numeric_std.ALL;
  4. USE work.POLY_FIR_PKG.ALL;
  5. PACKAGE simu_pkg IS
  6. TYPE donnee_sortie IS ARRAY (0 TO 200-1) OF integer;
  7. CONSTANT w_x_simu : natural := 4;
  8. END;