Polyphase_filter_vhdl/poly_shift_reg2.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.POLY_FIR_PKG.ALL;

ENTITY POLY_SHIFT_REG IS
  PORT(i_clk  : IN  std_logic;
       i_data : IN  vect_adc_data_out;
       o_data : OUT matrix3D_reg_data_out
       );
END POLY_SHIFT_REG;

ARCHITECTURE Fill_Matrix OF POLY_SHIFT_REG IS

  TYPE vect_i_data_temp IS ARRAY (0 TO cst_nb_subfilters-1) OF smpl_adc_data_in;
  TYPE matrix_i_data_temp IS ARRAY (0 TO 1) OF vect_i_data_temp;
  SIGNAL data_matrix : matrix3D_reg_data_out;
  --SIGNAL data_temp     : vect_reg_data := (OTHERS =>(OTHERS => '0'));
  SIGNAL data_temp   : matrix_reg_data := (OTHERS => (OTHERS => (OTHERS => '0')));
  --VARIABLE reg_i_data_temp : vect_i_data_temp := (OTHERS => (OTHERS => '0'));

BEGIN



  -- purpose: fill a 3D matrix from a register. Each row is the input of the
  -- input of a partial filter; each 2D matrix rows-columns is the input for a
  -- subfilter
  -- inputs:  reg_i_data_temp, i_data
  -- outputs: data_temp (3D matrix of std_logic_vectors)
  PROCESS (i_clk) IS
    VARIABLE subfilter_nb      : natural            := 0;
    VARIABLE data_subfilter_nb : natural            := 0;
    VARIABLE reg_i_data_temp   : matrix_i_data_temp;
  BEGIN  -- PROCESS
    IF rising_edge(i_clk) THEN          -- rising clock edge



      -- shifting the old samples towards data_temp(0)
      FOR i IN 0 TO cst_nb_subfilters-1 LOOP
        data_temp(i)(0 TO cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs-1) <= data_temp(i)(cst_nb_parallel_firs TO cst_nb_samples_shiftreg_temp_in-1);
      END LOOP;  -- i



      -- fill a temp 2D matrix for each subfilter (equivalent to filling a temp
      -- vector for 1 filter)
      parallel_fir_for : FOR parallel_fir_nb IN 0 TO cst_nb_parallel_firs-1 LOOP

        FOR i IN 0 TO cst_nb_subfilters-1 LOOP
          reg_i_data_temp(1) := reg_i_data_temp(0);
        END LOOP;
        fill_previous_content : FOR data_nb IN cst_downsampling_factor TO cst_nb_subfilters-1 LOOP
          data_temp(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= reg_i_data_temp(1)(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters));
        END LOOP fill_previous_content;  -- data_nb
        fill_data_temp : FOR data_nb IN 0 TO cst_downsampling_factor-1 LOOP  -- fill data
          data_temp(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= i_data(cst_downsampling_factor*parallel_fir_nb+data_nb);
          reg_i_data_temp(0)(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters))                                                              := i_data(cst_downsampling_factor*parallel_fir_nb+data_nb);

        END LOOP fill_data_temp;
      END LOOP parallel_fir_for;  -- parallel_fir_nb

      o_data <= data_matrix;

    END IF;
  END PROCESS;



  -- purpose: wiring (filling the 3D out matrix) for each line, for each subfilter
  third_dimension : FOR subfilter_nb IN 0 TO cst_nb_subfilters-1 GENERATE
    second_dimension : FOR parallel_fir IN 0 TO cst_nb_parallel_firs-1 GENERATE
      first_dimension : FOR data_nb IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
        data_matrix(subfilter_nb)(parallel_fir)(data_nb) <= data_temp(subfilter_nb)(data_nb+parallel_fir);
      END GENERATE first_dimension;  -- data_nb
    END GENERATE second_dimension;  -- parallel_fir
  END GENERATE third_dimension;  -- subfilter_nb

END Fill_Matrix;