Simulation files of Polyphase Filter in VHDL for FPGA.
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- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
- USE ieee.numeric_std.ALL;
- USE work.POLY_FIR_PKG.ALL;
-
- ENTITY MULT_BLK IS
- PORT(i_clk : IN std_logic;
- i_data : IN vect_fir_data_in;
- i_coeffs : IN vect_fir_coeffs_in;
- o_data : OUT vect_mult_data_out
- );
- END MULT_BLK;
-
- ARCHITECTURE Mult_Path OF MULT_BLK IS
-
- SIGNAL data_mult_signed : vect_mult_data_out_signed;
- SIGNAL coeffs_signed : vect_mult_coeffs_signed;
- SIGNAL data_signed : vect_data_mult_in_signed;
-
-
- BEGIN
-
- -- purpose: wiring: cast the i_data and i_coeffs into signed
- cast : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
- data_signed(i) <= signed(i_data(i));
- coeffs_signed(i) <= signed(i_coeffs(i));
- END GENERATE cast;
-
-
-
- -- purpose: calculate and send cast result to output
- mult : PROCESS(i_clk)
- BEGIN
- IF rising_edge(i_clk) THEN
- FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 LOOP
- data_mult_signed(i) <= data_signed(i) * coeffs_signed(i);
- o_data(i) <= std_logic_vector(unsigned(data_mult_signed(i)));
- END LOOP;
- END IF;
- END PROCESS;
-
- END Mult_Path;
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