Polyphase_filter_vhdl/add_blk.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.POLY_FIR_PKG.ALL;

ENTITY add_blk IS
  GENERIC(w_out : IN natural);
  PORT(i_clk   : IN  std_logic;
       i_data1 : IN  smpl_adder_generic;
       i_data2 : IN  smpl_adder_generic;
       o_data  : OUT smpl_fir_adder_data_out
       );
END add_blk;

ARCHITECTURE add OF add_blk IS

  SIGNAL smpl_stages_out : smpl_adder_generic := (OTHERS => '0');

BEGIN  -- ARCHITECTURE add

  -- purpose: creates the add process for the adding tree
  -- type   : sequential
  -- inputs : i_clk, i_data1, i_data2
  -- outputs: o_data
  adding_process : PROCESS (i_clk) IS
  BEGIN  -- PROCESS adding_process
    IF rising_edge(i_clk) THEN          -- rising clock edge
      smpl_stages_out(w_out DOWNTO 0) <= std_logic_vector(unsigned(signed(i_data1(w_out-1)&i_data1(w_out-1 DOWNTO 0))+signed(i_data2(w_out-1)&i_data2(w_out-1 DOWNTO 0))));
    END IF;
  END PROCESS adding_process;

  o_data <= smpl_stages_out;

END ARCHITECTURE add;