Transférer les fichiers vers ''

poly_shift_reg.vhd

@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+ENTITY POLY_SHIFT_REG IS
+  PORT(i_clk  : IN  std_logic;
+       i_data : IN  vect_adc_data_out;
+       o_data : OUT matrix3D_reg_data_out
+       );
+END POLY_SHIFT_REG;
+
+ARCHITECTURE Fill_Matrix OF POLY_SHIFT_REG IS
+
+  TYPE vect_i_data_temp IS ARRAY (0 TO cst_nb_subfilters-1) OF smpl_adc_data_in;
+  SIGNAL data_matrix     : matrix3D_reg_data_out;
+  --SIGNAL data_temp     : vect_reg_data := (OTHERS =>(OTHERS => '0'));
+  SIGNAL data_temp       : matrix_reg_data  := (OTHERS => (OTHERS => (OTHERS => '0')));
+  SIGNAL reg_i_data_temp : vect_i_data_temp := (OTHERS => (OTHERS => '0'));
+
+BEGIN
+
+
+
+  -- purpose: fill a 3D matrix from a register. Each row is the input of the
+  -- input of a partial filter; each 2D matrix rows-columns is the input for a
+  -- subfilter
+  -- inputs:  reg_i_data_temp, i_data
+  -- outputs: data_temp (3D matrix of std_logic_vectors)
+  PROCESS (i_clk) IS
+    VARIABLE subfilter_nb      : natural := 0;
+    VARIABLE data_subfilter_nb : natural := 0;
+  BEGIN  -- PROCESS
+    IF rising_edge(i_clk) THEN          -- rising clock edge
+
+
+
+      -- add the new data to the register
+      FOR i IN 0 TO cst_nb_subfilters-1 LOOP  -- register to store previous data
+        reg_i_data_temp(i) <= i_data(cst_nb_samples_adc_in-cst_nb_subfilters+i);
+      END LOOP;  -- i
+      -- shifting the old samples towards reg_i_data_temp(0)
+      FOR i IN 0 TO cst_nb_subfilters-1 LOOP
+        data_temp(i)(0 TO cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs-1) <= data_temp(i)(cst_nb_parallel_firs TO cst_nb_samples_shiftreg_temp_in-1);
+      END LOOP;  -- i
+
+
+
+      -- fill a temp 2D matrix for each subfilter (equivalent to filling a temp
+      -- vector for 1 filter)
+      parallel_fir_for : FOR parallel_fir_nb IN 0 TO cst_nb_parallel_firs-1 LOOP
+        fill_data_temp : FOR data_nb IN 0 TO cst_nb_subfilters-1 LOOP  -- fill data and copy previous content
+
+          IF(data_nb < cst_downsampling_factor) THEN
+            data_temp(cst_nb_subfilters-1-((parallel_fir_nb*cst_downsampling_factor+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= i_data(cst_downsampling_factor*parallel_fir_nb+data_nb);
+          ELSE
+            IF((parallel_fir_nb*cst_downsampling_factor+data_nb)-cst_nb_subfilters < 0) THEN
+              data_temp(cst_nb_subfilters-1-((parallel_fir_nb*cst_downsampling_factor+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= reg_i_data_temp(data_nb);
+            ELSE
+              data_temp(cst_nb_subfilters-1-((parallel_fir_nb*cst_downsampling_factor+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= i_data(cst_downsampling_factor*parallel_fir_nb+data_nb-cst_nb_subfilters);
+            END IF;
+          END IF;
+
+        END LOOP fill_data_temp;
+      END LOOP parallel_fir_for;  -- parallel_fir_nb
+
+      o_data <= data_matrix;
+
+    END IF;
+  END PROCESS;
+
+
+
+  -- purpose: wiring (filling the 3D out matrix) for each line, for each subfilter
+  third_dimension : FOR subfilter_nb IN 0 TO cst_nb_subfilters-1 GENERATE
+    second_dimension : FOR parallel_fir IN 0 TO cst_nb_parallel_firs-1 GENERATE
+      first_dimension : FOR data_nb IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
+        data_matrix(subfilter_nb)(parallel_fir)(data_nb) <= data_temp(subfilter_nb)(data_nb+parallel_fir);
+      END GENERATE first_dimension;  -- data_nb
+    END GENERATE second_dimension;  -- parallel_fir
+  END GENERATE third_dimension;  -- subfilter_nb
+
+END Fill_Matrix;

simu_pkg.vhd

@@ -0,0 +1,13 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+PACKAGE simu_pkg IS
+
+
+  TYPE donnee_sortie IS ARRAY (0 TO 200-1) OF integer;
+  CONSTANT w_x_simu : natural := 4;
+
+
+END;

tree_fir.vhd

@@ -0,0 +1,31 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+ENTITY TREE_FIR IS
+  PORT(	i_clk 	 : IN std_logic;
+        i_coeffs : IN vect_fir_coeffs_in;
+        i_data 	 : IN matrix_reg_data_out;
+        o_data	 : OUT vect_fir_data_out
+        );
+END TREE_FIR;
+
+ARCHITECTURE Simple_Fir OF TREE_FIR IS
+
+  SIGNAL partial_fir_out : vect_fir_adder_data_out := (OTHERS => (OTHERS => '0'));
+
+BEGIN
+
+  -- purpose: wiring: instanciation of each partial FIR to make 1 FIR
+  partial_fir_for : FOR i IN 0 TO cst_nb_parallel_firs-1 GENERATE
+    partial_fir_inst : ENTITY work.PARTIAL_FIR(Adder_Tree)
+      PORT MAP(	i_clk  	 => i_clk,
+                i_coeffs => i_coeffs,
+                i_data 	 => i_data(i),
+                o_data	 => partial_fir_out(i)
+		);
+    o_data(i)<= partial_fir_out(i)(cst_w_fir_adder_out-1 DOWNTO cst_w_fir_adder_out-cst_w_out);
+  END GENERATE partial_fir_for;
+
+
+END Simple_Fir;

utils.vhd

@@ -0,0 +1,33 @@
+-- *********************** Divers fonction utiles ***************************
+
+
+LIBRARY ieee; 
+USE ieee.std_logic_1164.ALL;
+
+
+PACKAGE utils IS
+  PROCEDURE horloge ( SIGNAL h: OUT std_logic; th, tb : time); 
+  PROCEDURE horloge_retard ( SIGNAL h : OUT std_logic; periode : time ;
+                             retard : time); 
+END utils;
+---------------------------------------------------
+PACKAGE BODY utils IS
+  PROCEDURE horloge ( SIGNAL h : OUT std_logic; th, tb : time) IS 
+  BEGIN 
+    LOOP 
+      h <= '0', '1' AFTER tb; 
+      WAIT FOR tb + th ; 
+    END LOOP; 
+  END;
+  
+  PROCEDURE horloge_retard ( SIGNAL h : OUT std_logic; periode : time ;
+                             retard : time) IS 
+  BEGIN 
+    h <= '0'; 
+    WAIT FOR retard; 
+    LOOP 
+      h <= '1' , '0' AFTER periode/2 ; 
+      WAIT FOR periode; 
+    END LOOP; 
+  END; 
+END utils;