Merge pull request 'testing' (#1) from testing into master

add_blk.vhd

@@ -0,0 +1,34 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+ENTITY add_blk IS
+  GENERIC(w_out : IN natural);
+  PORT(i_clk   : IN  std_logic;
+       i_data1 : IN  smpl_adder_generic;
+       i_data2 : IN  smpl_adder_generic;
+       o_data  : OUT smpl_fir_adder_data_out
+       );
+END add_blk;
+
+ARCHITECTURE add OF add_blk IS
+
+  SIGNAL smpl_stages_out : smpl_adder_generic := (OTHERS => '0');
+
+BEGIN  -- ARCHITECTURE add
+
+  -- purpose: creates the add process for the adding tree
+  -- type   : sequential
+  -- inputs : i_clk, i_data1, i_data2
+  -- outputs: o_data
+  adding_process : PROCESS (i_clk) IS
+  BEGIN  -- PROCESS adding_process
+    IF rising_edge(i_clk) THEN          -- rising clock edge
+      smpl_stages_out(w_out DOWNTO 0) <= std_logic_vector(unsigned(signed(i_data1(w_out-1)&i_data1(w_out-1 DOWNTO 0))+signed(i_data2(w_out-1)&i_data2(w_out-1 DOWNTO 0))));
+    END IF;
+  END PROCESS adding_process;
+
+  o_data <= smpl_stages_out;
+
+END ARCHITECTURE add;

mult_blk.vhd

@@ -0,0 +1,42 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+ENTITY MULT_BLK IS
+  PORT(i_clk    : IN  std_logic;
+       i_data   : IN  vect_fir_data_in;
+       i_coeffs : IN  vect_fir_coeffs_in;
+       o_data   : OUT vect_mult_data_out
+       );
+END MULT_BLK;
+
+ARCHITECTURE Mult_Path OF MULT_BLK IS
+
+  SIGNAL data_mult_signed : vect_mult_data_out_signed;
+  SIGNAL coeffs_signed    : vect_mult_coeffs_signed;
+  SIGNAL data_signed      : vect_data_mult_in_signed;
+
+
+BEGIN
+
+  -- purpose: wiring: cast the i_data and i_coeffs into signed
+  cast : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
+    data_signed(i)   <= signed(i_data(i));
+    coeffs_signed(i) <= signed(i_coeffs(i));
+  END GENERATE cast;
+
+
+
+  -- purpose: calculate and send cast result to output
+  mult : PROCESS(i_clk)
+  BEGIN
+    IF rising_edge(i_clk) THEN
+      FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 LOOP
+        data_mult_signed(i) <= data_signed(i) * coeffs_signed(i);
+        o_data(i) <= std_logic_vector(unsigned(data_mult_signed(i)));
+      END LOOP;
+    END IF;
+  END PROCESS;
+
+END Mult_Path;

partial_fir.vhd

@@ -0,0 +1,85 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+USE work.POLY_FIR_PKG.ALL;
+
+ENTITY PARTIAL_FIR IS
+  PORT(i_clk    : IN  std_logic;
+       i_coeffs : IN  vect_fir_coeffs_in;
+       i_data   : IN  vect_fir_data_in;
+       o_data   : OUT smpl_fir_adder_data_out
+       );
+END PARTIAL_FIR;
+
+ARCHITECTURE Adder_Tree OF PARTIAL_FIR IS
+
+  SIGNAL matrix_adder_tree : matrix_adder_generic := (OTHERS => (OTHERS => (OTHERS => '0')));
+  --SIGNAL matrix_adder_tree_signed : matrix_adder_generic_signed := (OTHERS => (OTHERS => (OTHERS => '0')));
+  SIGNAL vect_i_coeffs     : vect_fir_coeffs_in;
+  SIGNAL mult_out          : vect_mult_data_out   := (OTHERS => (OTHERS => '0'));
+
+BEGIN
+
+
+
+  -- purpose: assign the filter in a decreasing order
+  in_assignment : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
+    vect_i_coeffs(i) <= i_coeffs(cst_nb_coeffs_subfilter_in-1-i);
+  END GENERATE in_assignment;
+
+
+
+  -- instanciation of MULT_BLK(Mult_Path), multiplying each element from i_data
+  -- with the correct coefficient in vect_i_coeffs
+  mult_inst : ENTITY work.MULT_BLK(Mult_Path)
+    PORT MAP(i_clk    => i_clk,
+             i_data   => i_data,
+             i_coeffs => vect_i_coeffs,
+             o_data   => mult_out
+             );
+
+
+
+  -- purpose: fill the input (which is the result of multiplication) of the addition tree matrix
+  -- inputs: mult_out
+  -- outputs:  matrix_adder_tree(0)
+  mult_out_wire : FOR i IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
+    matrix_adder_tree(0)(i)(cst_w_mult_out-1 DOWNTO 0) <= mult_out(i)(cst_w_mult_out-1 DOWNTO 0);
+  END GENERATE mult_out_wire;
+
+
+
+  -- purpose: wiring: construct the adder tree. Construction:
+  --
+  -- 0-+--+----+->
+  -- 1/  /    /
+  -- 2-+/    /
+  -- 3/     /
+  -- 4-+--+/
+  -- 5/  /
+  -- 6-+/
+  -- 7/
+  --
+  -- inputs: matrix_adder_tree(0)
+  -- outputs: matrix_adder_tree(cst_log2_adder_stages)
+  stages_loop : FOR stage IN 1 TO cst_log2_adder_stages GENERATE
+    cell_loops : FOR cell IN 0 TO 2**(cst_log2_adder_stages-stage)-1 GENERATE
+
+       add_inst : ENTITY work.add_blk(add)
+        GENERIC MAP(w_out => cst_w_mult_out+stage-1)
+        PORT MAP(i_clk   => i_clk,
+                 i_data1 => matrix_adder_tree(stage-1)((2**(stage-1))*2*cell),
+                 i_data2 => matrix_adder_tree(stage-1)((2**(stage-1))*(2*cell+1)),
+                 o_data  => matrix_adder_tree(stage)((2**stage)*cell)
+                 );
+
+    END GENERATE cell_loops;
+  END GENERATE stages_loop;
+
+
+
+-- take the result when adder tree finished
+  o_data <= matrix_adder_tree(cst_log2_adder_stages)(0);
+
+END Adder_Tree;

poly_fir_blk.vhd

@@ -0,0 +1,73 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+
+
+ENTITY poly_fir_blk IS
+
+  PORT (
+    i_clk    : IN  std_logic;
+    i_coeffs : IN  vect_polyfir_coeffs_in;
+    i_data   : IN  vect_adc_data_out;
+    o_data   : OUT matrix_fir_data_out);
+
+END ENTITY poly_fir_blk;
+
+ARCHITECTURE polyphase OF poly_fir_blk IS
+
+  SIGNAL matrix3D_reg_out_simple_rif_in : matrix3D_reg_data_out := (OTHERS => (OTHERS => (OTHERS => (OTHERS => '0'))));
+  SIGNAL matrix_coeffs                  : matrix_fir_coeffs_in  := (OTHERS => (OTHERS => (OTHERS => '0')));
+  SIGNAL matrix_fir_out                 : matrix_fir_data_out   := (OTHERS => (OTHERS => (OTHERS => '0')));
+
+
+BEGIN  -- ARCHITECTURE polyphase
+
+
+
+  --purpose: fill the polyphase coefficients into a 2D matrix from the filter vector (1D)
+  fill_coeff : PROCESS(i_coeffs)        -- rearrange coeffs into a matrix
+    VARIABLE coeff_nb     : natural;
+    VARIABLE sf_coeff     : natural;
+    VARIABLE subfilter_nb : natural;
+  BEGIN
+    coeff_nb     := 0;
+    sf_coeff     := 0;
+    subfilter_nb := 0;
+    coeff_for_matrix : FOR coeff_nb IN 0 TO cst_nb_coeffs_filter_in-1 LOOP
+      matrix_coeffs(subfilter_nb)(sf_coeff) <= i_coeffs(coeff_nb);
+      subfilter_nb                          := subfilter_nb+1;
+      IF (subfilter_nb = cst_nb_subfilters) THEN
+        sf_coeff     := sf_coeff+1;
+        subfilter_nb := 0;
+      END IF;
+    END LOOP coeff_for_matrix;
+  END PROCESS fill_coeff;
+
+
+
+  -- instanciation of the shift-reg for polyphasd filter
+  shift_reg_inst : ENTITY work.POLY_SHIFT_REG(Fill_Matrix)
+    PORT MAP (i_clk  => i_clk,
+              i_data => i_data,
+              o_data => matrix3D_reg_out_simple_rif_in
+              );
+
+
+
+  -- instanciation of the cst_nb_subfilters subfilters
+  simple_fir_inst_loop : FOR i IN 0 TO cst_nb_subfilters-1 GENERATE
+    simple_fir_inst : ENTITY work.TREE_FIR(Simple_Fir)
+      PORT MAP(i_clk    => i_clk,
+               i_coeffs => matrix_coeffs(i),
+               i_data   => matrix3D_reg_out_simple_rif_in(i),
+               o_data   => matrix_fir_out(i)
+               );
+  END GENERATE simple_fir_inst_loop;
+
+
+
+
+  o_data <= matrix_fir_out;
+
+END ARCHITECTURE polyphase;

poly_fir_pkg.vhd

@@ -0,0 +1,200 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE ieee.std_logic_unsigned.ALL;
+USE ieee.std_logic_signed.ALL;
+
+PACKAGE POLY_FIR_PKG IS
+
+  -- NOTES and PACKAGE INSTRUCTIONS :
+  -- cst_downsampling_factor must be a multiplier OF cst_nb_samples_adc_in
+  -- and cst_nb_subfilters/cst_nb_samples_adc_in*cst_downsampling_factor must be an integer
+  -- with cst_downsampling_factor < or = cst_nb_subfilters.
+  --
+  -- INPUT  : vector of samples (cst_nb_samples_adc_in samples);
+  -- OUTPUT : 2D matrix of samples (matrix_fir_data_out(y)(x), with y the
+  -- subfilter number, and x the xth parallel fir);
+  --
+  -- the lower parallel fir, the older result.
+
+
+
+  FUNCTION log2_sup_integer (number : natural) RETURN natural;
+  FUNCTION log2_inf_integer (number : natural) RETURN natural;
+
+  -- -- CONSTANTS -- --
+
+  -- ADC
+  CONSTANT cst_w_in  : natural := 6;    -- ADC in bitwidth
+
+  CONSTANT cst_nb_samples_adc_in : natural := 80;  -- ADC in nb samples
+
+  -- FILTER
+  --coefficients
+  CONSTANT cst_w_coeff                         : natural := 8;  -- coeffs bitwidth
+  CONSTANT cst_nb_coeffs_filter_in             : natural := 7*20;
+  CONSTANT cst_log2_sup_nb_coeffs_subfilter_in : natural := 3;
+
+  -- FIR
+  CONSTANT cst_downsampling_factor : natural := 8;
+  -- POLYPHASE FILTER
+  CONSTANT cst_nb_subfilters       : natural := 20;
+  
+
+  -- -- CALCULATIONS -- --
+
+  CONSTANT cst_w_out : natural := cst_w_in + cst_w_coeff+cst_log2_sup_nb_coeffs_subfilter_in;
+
+  -- SHIFT REG
+
+  CONSTANT cst_nb_coeffs_subfilter_in      : natural := cst_nb_coeffs_filter_in/cst_nb_subfilters;
+  CONSTANT cst_nb_samples_shiftreg_temp_in : natural := cst_nb_coeffs_subfilter_in + cst_nb_samples_adc_in/cst_downsampling_factor;
+  -- mult
+  CONSTANT cst_w_mult_out                  : natural := cst_w_coeff+cst_w_in;
+  -- adder
+  CONSTANT cst_log2_adder_stages           : natural := cst_log2_sup_nb_coeffs_subfilter_in;
+  -- fir
+  CONSTANT cst_w_fir_adder_out             : natural := cst_w_mult_out+cst_log2_adder_stages;
+  CONSTANT cst_nb_parallel_firs            : natural := cst_nb_samples_adc_in/cst_downsampling_factor;
+
+  -- TYPES
+
+  -- ADC
+  SUBTYPE smpl_adc_data_in IS std_logic_vector(cst_w_in-1 DOWNTO 0);
+  SUBTYPE smpl_fir_data_out IS std_logic_vector(cst_w_out-1 DOWNTO 0);
+
+
+  -- SHIFT REG
+
+  TYPE vect_adc_data_out IS ARRAY (0 TO cst_nb_samples_adc_in-1) OF smpl_adc_data_in;
+  TYPE vect_fir_data_in IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_adc_data_in;
+  TYPE vect_reg_data IS ARRAY(0 TO cst_nb_samples_shiftreg_temp_in-1) OF smpl_adc_data_in;
+  TYPE matrix_reg_data IS ARRAY(0 TO cst_nb_subfilters-1) OF vect_reg_data;
+
+  TYPE matrix_reg_data_out IS ARRAY(0 TO cst_nb_parallel_firs-1) OF vect_fir_data_in;
+  TYPE matrix3D_reg_data_out IS ARRAY (0 TO cst_nb_subfilters-1) OF matrix_reg_data_out;
+
+  -- FILTER
+
+  SUBTYPE smpl_coeff IS std_logic_vector(cst_w_coeff-1 DOWNTO 0);
+
+  -- mult
+  SUBTYPE smpl_mult_data_out IS std_logic_vector(cst_w_mult_out-1 DOWNTO 0);
+  SUBTYPE smpl_mult_data_out_signed IS signed(cst_w_mult_out-1 DOWNTO 0);
+  SUBTYPE smpl_coeffs_signed IS signed(cst_w_coeff-1 DOWNTO 0);
+  SUBTYPE smpl_mult_data_in_signed IS signed(cst_w_in-1 DOWNTO 0);
+  TYPE vect_polyfir_coeffs_in IS ARRAY (0 TO cst_nb_coeffs_filter_in-1) OF smpl_coeff;
+  TYPE vect_data_mult_in_signed IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_mult_data_in_signed;
+  TYPE vect_fir_coeffs_in IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_coeff;
+  TYPE vect_mult_coeffs_signed IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_coeffs_signed;
+  TYPE vect_mult_data_out IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_mult_data_out;
+  TYPE vect_mult_data_out_signed IS ARRAY(0 TO cst_nb_coeffs_subfilter_in-1) OF smpl_mult_data_out_signed;
+  TYPE matrix_fir_coeffs_in IS ARRAY (0 TO cst_nb_subfilters-1) OF vect_fir_coeffs_in;
+
+  -- adder
+  SUBTYPE smpl_adder_generic IS std_logic_vector(cst_w_fir_adder_out-1 DOWNTO 0);
+  SUBTYPE smpl_adder_generic_signed IS signed(cst_w_fir_adder_out-1 DOWNTO 0);
+  TYPE vect_adder_generic IS ARRAY(0 TO 2**(cst_log2_adder_stages)-1) OF smpl_adder_generic;
+  TYPE vect_adder_generic_signed IS ARRAY(0 TO 2**(cst_log2_adder_stages)-1) OF smpl_adder_generic_signed;
+  TYPE matrix_adder_generic IS ARRAY(0 TO cst_log2_adder_stages) OF vect_adder_generic;
+  TYPE matrix_adder_generic_signed IS ARRAY(0 TO cst_log2_adder_stages) OF vect_adder_generic_signed;
+
+  -- fir
+  SUBTYPE smpl_fir_adder_data_out IS std_logic_vector(cst_w_fir_adder_out-1 DOWNTO 0);
+  TYPE vect_fir_adder_data_out IS ARRAY (0 TO cst_nb_parallel_firs-1) OF smpl_fir_adder_data_out;
+  TYPE vect_fir_data_out IS ARRAY(0 TO cst_nb_parallel_firs-1) OF smpl_fir_data_out;
+
+  -- POLYPHASE FILTER
+
+  TYPE matrix_fir_data_out IS ARRAY (0 TO cst_nb_subfilters-1) OF vect_fir_data_out;
+  -- TYPE matrix_coeffs_polyphase_filter                IS array(0 to cst_nb_subfilters) OF vect_mult_coeffs;
+
+
+
+
+
+END;
+
+PACKAGE BODY POLY_FIR_PKG IS
+
+
+  --functions
+  FUNCTION log2_sup_integer (number : natural) RETURN natural IS
+    VARIABLE result : natural;
+  BEGIN
+
+    IF(number <= 1) THEN
+      result := 0;
+    ELSIF(number = 2) THEN
+      result := 1;
+    ELSIF(number > 2 AND number <= 4) THEN
+      result := 2;
+    ELSIF(number > 4 AND number <= 8) THEN
+      result := 3;
+    ELSIF(number > 8 AND number <= 16) THEN
+      result := 4;
+    ELSIF(number > 16 AND number <= 32) THEN
+      result := 5;
+    ELSIF(number > 32 AND number <= 64) THEN
+      result := 6;
+    ELSIF(number > 64 AND number <= 128) THEN
+      result := 7;
+    ELSIF(number > 128 AND number <= 256) THEN
+      result := 8;
+    ELSIF(number > 256 AND number <= 512) THEN
+      result := 9;
+    ELSIF(number > 512 AND number <= 1024) THEN
+      result := 10;
+    ELSIF(number > 1024 AND number <= 2048) THEN
+      result := 11;
+    ELSIF(number > 2048 AND number <= 4096) THEN
+      result := 12;
+    ELSIF(number > 4096 AND number <= 8192) THEN
+      result := 13;
+    ELSIF(number > 8192 AND number <= 16384) THEN
+      result := 14;
+    ELSIF(number > 16384 AND number <= 32768) THEN
+      result := 15;
+    END IF;
+    RETURN result;
+  END FUNCTION;
+
+  FUNCTION log2_inf_integer (number : natural) RETURN natural IS
+    VARIABLE result : natural;
+  BEGIN
+
+    IF(number < 2) THEN
+      result := 0;
+    ELSIF(number >= 2 AND number < 4) THEN
+      result := 1;
+    ELSIF(number >= 4 AND number < 8) THEN
+      result := 2;
+    ELSIF(number >= 8 AND number < 16) THEN
+      result := 3;
+    ELSIF(number >= 16 AND number < 32) THEN
+      result := 4;
+    ELSIF(number >= 32 AND number < 64) THEN
+      result := 5;
+    ELSIF(number >= 64 AND number < 128) THEN
+      result := 6;
+    ELSIF(number >= 128 AND number < 256) THEN
+      result := 7;
+    ELSIF(number >= 256 AND number < 512) THEN
+      result := 8;
+    ELSIF(number >= 512 AND number < 1024) THEN
+      result := 9;
+    ELSIF(number >= 1024 AND number < 2048) THEN
+      result := 10;
+    ELSIF(number >= 2048 AND number < 4096) THEN
+      Result := 11;
+    ELSIF(Number >= 4096 AND number < 8192) THEN
+      result := 12;
+    ELSIF(number >= 8192 AND number < 16384) THEN
+      result := 13;
+    ELSIF(number >= 16384 AND number < 32768) THEN
+      result := 14;
+    END IF;
+    RETURN result;
+  END FUNCTION;
+
+END PACKAGE BODY;

poly_fir_tb.vhd

@@ -0,0 +1,141 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE work.POLY_FIR_PKG.ALL;
+USE work.simu_pkg.ALL;
+USE work.utils.ALL;
+LIBRARY std;
+USE std.textio.ALL;
+USE work.coeff.ALL;
+
+ENTITY poly_fir_tb IS
+
+  GENERIC (
+    demi_periode : time   := 5 ns;
+-- duree de la demi periode des horloges
+    test_e       : string := "D:\Stage\ALMA_OPFB\simu\polyphase_fir - v0.2\tb_txts_files\input.txt";
+-- fichier test contenant les echantillons d'entree
+
+    test_s : string := "D:\Stage\ALMA_OPFB\simu\polyphase_fir - v0.2\tb_txts_files\output.txt"
+-- fichier contenant les echantillons de sortie
+
+    --fir_addr : std_logic_vector(band5a_w_fc-1 DOWNTO 0) := std_logic_vector(unsigned(band5a_fc_index, band5a_w_fc))
+
+-- coeff de décimation
+    );
+
+END poly_fir_tb;
+
+ARCHITECTURE beh OF poly_fir_tb IS
+  TYPE vect_from_matrix_fir_data_out IS ARRAY (0 TO cst_nb_subfilters*cst_nb_parallel_firs-1) OF smpl_fir_data_out;
+  FILE fichier_e : text IS IN test_e;
+  FILE fichier_s : text IS IN test_s;
+  --FILE fichier_c : text IS IN test_c;
+
+  SIGNAL initialisation      : std_logic;
+  SIGNAL h                   : std_logic;
+  SIGNAL entree_fir          : vect_adc_data_out             := (OTHERS => (OTHERS => '0'));
+  SIGNAL sortie_fir          : vect_from_matrix_fir_data_out := (OTHERS => (OTHERS => '0'));
+  SIGNAL sortie_fir_sim      : matrix_fir_data_out           := (OTHERS => (OTHERS => (OTHERS => '0')));
+  --SIGNAL coeffs_fir     : vect_fir_coeffs_in := ;
+  SIGNAL sortie_fir_sim_vect : vect_from_matrix_fir_data_out := (OTHERS => (OTHERS => '0'));
+  SIGNAL verif               : donnee_sortie;
+
+
+BEGIN  -- ARCHITECTURE beh
+  module_simu : ENTITY work.poly_fir_blk(polyphase)
+    PORT MAP(h, fir_coeffs_generated, entree_fir, sortie_fir_sim);
+
+  horloge_entree : horloge(h, demi_periode, demi_periode);
+
+  sortie_fir_sim_process : PROCESS(sortie_fir_sim)
+    VARIABLE mots_lignes : natural := cst_nb_parallel_firs;
+  BEGIN
+    FOR k IN 0 TO mots_lignes-1 LOOP
+      FOR j IN 0 TO cst_nb_subfilters-1 LOOP
+        sortie_fir_sim_vect(k*cst_nb_subfilters+j) <= sortie_fir_sim(j)(k);
+      END LOOP;
+    END LOOP;
+  END PROCESS;
+
+  source : PROCESS
+    CONSTANT header     : natural := 1;      -- nombre de ligne d'en tête
+    CONSTANT nbr_ech    : natural := 800000;  -- nombre d'echantillons d'entree dans le fichier test 
+    CONSTANT mots_ligne : natural := cst_nb_samples_adc_in;  -- nombre de mots par ligne dans le ficher
+    VARIABLE nbr_ligne  : natural := 10000;  --2750;  --15625;  -- nombre de lignes restant à lire dans le fichier
+    VARIABLE i          : natural := 1;
+    VARIABLE donnee     : integer;
+    VARIABLE tempo      : natural := 0;
+    VARIABLE ligne      : line;
+    VARIABLE head       : boolean := false;
+
+  BEGIN  -- PROCESS source 
+
+    WAIT UNTIL falling_edge(h);
+
+    IF head = true THEN
+      head := false;
+      FOR i IN 0 TO header-1 LOOP
+        readline(fichier_e, ligne);
+      END LOOP;
+    END IF;
+
+    IF tempo > 0 THEN                   -- temps de synchro
+      tempo := tempo -1;
+
+    ELSIF nbr_ligne > 0 THEN
+
+      readline(fichier_e, ligne);
+      nbr_ligne := nbr_ligne-1;
+
+      FOR k IN 0 TO mots_ligne -1 LOOP
+        read(ligne, donnee);
+        entree_fir(k) <= std_logic_vector(to_signed(donnee, cst_w_in));
+      END LOOP;  -- k
+
+    END IF;
+
+  END PROCESS source;
+
+
+  test : PROCESS
+    CONSTANT header     : natural := 1;    -- nombre de ligne d'en tête
+    CONSTANT nbr_ech    : natural := 2000000;  --nombre d'echantillons d'entree dans le fichier test
+    CONSTANT mots_ligne : natural := 200;  -- nombre de mots par ligne dans le ficher
+    VARIABLE nbr_ligne  : natural := 10000;  -- nombre de lignes restant à lire dans le fichier                              
+    VARIABLE i          : natural;
+    VARIABLE donnee     : donnee_sortie;
+    VARIABLE ligne      : line;
+    VARIABLE tempo      : natural := 8;
+    VARIABLE sortie     : integer;
+    VARIABLE head       : boolean := false;
+  BEGIN  -- PROCESS test 
+
+    WAIT UNTIL falling_edge(h);
+
+
+    IF tempo > 0 THEN                   -- temps de synchro
+      tempo := tempo -1;
+      ASSERT false REPORT "Attente_2 ... " SEVERITY note;
+
+    ELSIF nbr_ligne > 0 THEN
+      readline(fichier_s, ligne);
+      nbr_ligne := nbr_ligne-1;
+
+      FOR k IN 0 TO mots_ligne-1 LOOP
+        read(ligne, donnee(k));
+        sortie        := to_integer(signed(sortie_fir_sim_vect(k)));
+        sortie_fir(k) <= std_logic_vector(to_signed(donnee(k), cst_w_out));
+        verif(k)      <= sortie - donnee(k);
+        ASSERT verif(k) = 0 REPORT "Valeur fir FAUSSE"
+          SEVERITY error;
+      --ASSERT sortie /= donnee(k) REPORT "OK"
+      --  SEVERITY note;
+      END LOOP;  -- k
+    END IF;
+
+
+
+  END PROCESS test;
+
+END ARCHITECTURE beh;

poly_shift_reg.vhd

@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+ENTITY POLY_SHIFT_REG IS
+  PORT(i_clk  : IN  std_logic;
+       i_data : IN  vect_adc_data_out;
+       o_data : OUT matrix3D_reg_data_out
+       );
+END POLY_SHIFT_REG;
+
+ARCHITECTURE Fill_Matrix OF POLY_SHIFT_REG IS
+
+  TYPE vect_i_data_temp IS ARRAY (0 TO cst_nb_subfilters-1) OF smpl_adc_data_in;
+  SIGNAL data_matrix     : matrix3D_reg_data_out;
+  --SIGNAL data_temp     : vect_reg_data := (OTHERS =>(OTHERS => '0'));
+  SIGNAL data_temp       : matrix_reg_data  := (OTHERS => (OTHERS => (OTHERS => '0')));
+  SIGNAL reg_i_data_temp : vect_i_data_temp := (OTHERS => (OTHERS => '0'));
+
+BEGIN
+
+
+
+  -- purpose: fill a 3D matrix from a register. Each row is the input of the
+  -- input of a partial filter; each 2D matrix rows-columns is the input for a
+  -- subfilter
+  -- inputs:  reg_i_data_temp, i_data
+  -- outputs: data_temp (3D matrix of std_logic_vectors)
+  PROCESS (i_clk) IS
+    VARIABLE subfilter_nb      : natural := 0;
+    VARIABLE data_subfilter_nb : natural := 0;
+  BEGIN  -- PROCESS
+    IF rising_edge(i_clk) THEN          -- rising clock edge
+
+
+
+      -- add the new data to the register
+      FOR i IN 0 TO cst_nb_subfilters-1 LOOP  -- register to store previous data
+        reg_i_data_temp(i) <= i_data(cst_nb_samples_adc_in-cst_nb_subfilters+i);
+      END LOOP;  -- i
+      -- shifting the old samples towards reg_i_data_temp(0)
+      FOR i IN 0 TO cst_nb_subfilters-1 LOOP
+        data_temp(i)(0 TO cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs-1) <= data_temp(i)(cst_nb_parallel_firs TO cst_nb_samples_shiftreg_temp_in-1);
+      END LOOP;  -- i
+
+
+
+      -- fill a temp 2D matrix for each subfilter (equivalent to filling a temp
+      -- vector for 1 filter)
+      parallel_fir_for : FOR parallel_fir_nb IN 0 TO cst_nb_parallel_firs-1 LOOP
+        fill_data_temp : FOR data_nb IN 0 TO cst_nb_subfilters-1 LOOP  -- fill data and copy previous content
+
+          IF(data_nb < cst_downsampling_factor) THEN
+            data_temp(cst_nb_subfilters-1-((parallel_fir_nb*cst_downsampling_factor+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= i_data(cst_downsampling_factor*parallel_fir_nb+data_nb);
+          ELSE
+            IF((parallel_fir_nb*cst_downsampling_factor+data_nb)-cst_nb_subfilters < 0) THEN
+              data_temp(cst_nb_subfilters-1-((parallel_fir_nb*cst_downsampling_factor+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= reg_i_data_temp(data_nb);
+            ELSE
+              data_temp(cst_nb_subfilters-1-((parallel_fir_nb*cst_downsampling_factor+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= i_data(cst_downsampling_factor*parallel_fir_nb+data_nb-cst_nb_subfilters);
+            END IF;
+          END IF;
+
+        END LOOP fill_data_temp;
+      END LOOP parallel_fir_for;  -- parallel_fir_nb
+
+      o_data <= data_matrix;
+
+    END IF;
+  END PROCESS;
+
+
+
+  -- purpose: wiring (filling the 3D out matrix) for each line, for each subfilter
+  third_dimension : FOR subfilter_nb IN 0 TO cst_nb_subfilters-1 GENERATE
+    second_dimension : FOR parallel_fir IN 0 TO cst_nb_parallel_firs-1 GENERATE
+      first_dimension : FOR data_nb IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
+        data_matrix(subfilter_nb)(parallel_fir)(data_nb) <= data_temp(subfilter_nb)(data_nb+parallel_fir);
+      END GENERATE first_dimension;  -- data_nb
+    END GENERATE second_dimension;  -- parallel_fir
+  END GENERATE third_dimension;  -- subfilter_nb
+
+END Fill_Matrix;

poly_shift_reg2.vhd

@@ -0,0 +1,79 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+ENTITY POLY_SHIFT_REG IS
+  PORT(i_clk  : IN  std_logic;
+       i_data : IN  vect_adc_data_out;
+       o_data : OUT matrix3D_reg_data_out
+       );
+END POLY_SHIFT_REG;
+
+ARCHITECTURE Fill_Matrix OF POLY_SHIFT_REG IS
+
+  TYPE vect_i_data_temp IS ARRAY (0 TO cst_nb_subfilters-1) OF smpl_adc_data_in;
+  TYPE matrix_i_data_temp IS ARRAY (0 TO 1) OF vect_i_data_temp;
+  SIGNAL data_matrix : matrix3D_reg_data_out;
+  --SIGNAL data_temp     : vect_reg_data := (OTHERS =>(OTHERS => '0'));
+  SIGNAL data_temp   : matrix_reg_data := (OTHERS => (OTHERS => (OTHERS => '0')));
+  --VARIABLE reg_i_data_temp : vect_i_data_temp := (OTHERS => (OTHERS => '0'));
+
+BEGIN
+
+
+
+  -- purpose: fill a 3D matrix from a register. Each row is the input of the
+  -- input of a partial filter; each 2D matrix rows-columns is the input for a
+  -- subfilter
+  -- inputs:  reg_i_data_temp, i_data
+  -- outputs: data_temp (3D matrix of std_logic_vectors)
+  PROCESS (i_clk) IS
+    VARIABLE subfilter_nb      : natural            := 0;
+    VARIABLE data_subfilter_nb : natural            := 0;
+    VARIABLE reg_i_data_temp   : matrix_i_data_temp;
+  BEGIN  -- PROCESS
+    IF rising_edge(i_clk) THEN          -- rising clock edge
+
+
+
+      -- shifting the old samples towards data_temp(0)
+      FOR i IN 0 TO cst_nb_subfilters-1 LOOP
+        data_temp(i)(0 TO cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs-1) <= data_temp(i)(cst_nb_parallel_firs TO cst_nb_samples_shiftreg_temp_in-1);
+      END LOOP;  -- i
+
+
+
+      -- fill a temp 2D matrix for each subfilter (equivalent to filling a temp
+      -- vector for 1 filter)
+      parallel_fir_for : FOR parallel_fir_nb IN 0 TO cst_nb_parallel_firs-1 LOOP
+
+        FOR i IN 0 TO cst_nb_subfilters-1 LOOP
+          reg_i_data_temp(1) := reg_i_data_temp(0);
+        END LOOP;
+        fill_previous_content : FOR data_nb IN cst_downsampling_factor TO cst_nb_subfilters-1 LOOP
+          data_temp(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= reg_i_data_temp(1)(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters));
+        END LOOP fill_previous_content;  -- data_nb
+        fill_data_temp : FOR data_nb IN 0 TO cst_downsampling_factor-1 LOOP  -- fill data
+          data_temp(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= i_data(cst_downsampling_factor*parallel_fir_nb+data_nb);
+          reg_i_data_temp(0)(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters))                                                              := i_data(cst_downsampling_factor*parallel_fir_nb+data_nb);
+
+        END LOOP fill_data_temp;
+      END LOOP parallel_fir_for;  -- parallel_fir_nb
+
+      o_data <= data_matrix;
+
+    END IF;
+  END PROCESS;
+
+
+
+  -- purpose: wiring (filling the 3D out matrix) for each line, for each subfilter
+  third_dimension : FOR subfilter_nb IN 0 TO cst_nb_subfilters-1 GENERATE
+    second_dimension : FOR parallel_fir IN 0 TO cst_nb_parallel_firs-1 GENERATE
+      first_dimension : FOR data_nb IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
+        data_matrix(subfilter_nb)(parallel_fir)(data_nb) <= data_temp(subfilter_nb)(data_nb+parallel_fir);
+      END GENERATE first_dimension;  -- data_nb
+    END GENERATE second_dimension;  -- parallel_fir
+  END GENERATE third_dimension;  -- subfilter_nb
+
+END Fill_Matrix;

simu_pkg.vhd

@@ -0,0 +1,13 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+PACKAGE simu_pkg IS
+
+
+  TYPE donnee_sortie IS ARRAY (0 TO 200-1) OF integer;
+  CONSTANT w_x_simu : natural := 4;
+
+
+END;

tb_txt_files/coeff.vhd

@@ -0,0 +1,6 @@
+library ieee;
+USE ieee.std_logic_1164.all;
+USE work.POLY_FIR_PKG.all;
+package coeff is
+  CONSTANT fir_coeffs_generated : vect_polyfir_coeffs_in := (X"04",X"00",X"00",X"00",X"00",X"00",X"ff",X"ff",X"ff",X"fe",X"fe",X"fe",X"fd",X"fd",X"fc",X"fc",X"fb",X"fb",X"fa",X"fa",X"f9",X"f9",X"f9",X"f8",X"f8",X"f8",X"f7",X"f7",X"f7",X"f8",X"f8",X"f8",X"f9",X"f9",X"fa",X"fb",X"fc",X"fe",X"ff",X"01",X"02",X"04",X"07",X"09",X"0b",X"0e",X"10",X"13",X"16",X"19",X"1c",X"1f",X"22",X"25",X"27",X"2a",X"2d",X"30",X"32",X"35",X"37",X"39",X"3b",X"3d",X"3f",X"40",X"41",X"42",X"42",X"42",X"42",X"42",X"42",X"41",X"40",X"3f",X"3d",X"3b",X"39",X"37",X"35",X"32",X"30",X"2d",X"2a",X"27",X"25",X"22",X"1f",X"1c",X"19",X"16",X"13",X"10",X"0e",X"0b",X"09",X"07",X"04",X"02",X"01",X"ff",X"fe",X"fc",X"fb",X"fa",X"f9",X"f9",X"f8",X"f8",X"f8",X"f7",X"f7",X"f7",X"f8",X"f8",X"f8",X"f9",X"f9",X"f9",X"fa",X"fa",X"fb",X"fb",X"fc",X"fc",X"fd",X"fd",X"fe",X"fe",X"fe",X"ff",X"ff",X"ff",X"00",X"00",X"00",X"00",X"00",X"04");
+end package coeff;

tree_fir.vhd

@@ -0,0 +1,31 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+ENTITY TREE_FIR IS
+  PORT(	i_clk 	 : IN std_logic;
+        i_coeffs : IN vect_fir_coeffs_in;
+        i_data 	 : IN matrix_reg_data_out;
+        o_data	 : OUT vect_fir_data_out
+        );
+END TREE_FIR;
+
+ARCHITECTURE Simple_Fir OF TREE_FIR IS
+
+  SIGNAL partial_fir_out : vect_fir_adder_data_out := (OTHERS => (OTHERS => '0'));
+
+BEGIN
+
+  -- purpose: wiring: instanciation of each partial FIR to make 1 FIR
+  partial_fir_for : FOR i IN 0 TO cst_nb_parallel_firs-1 GENERATE
+    partial_fir_inst : ENTITY work.PARTIAL_FIR(Adder_Tree)
+      PORT MAP(	i_clk  	 => i_clk,
+                i_coeffs => i_coeffs,
+                i_data 	 => i_data(i),
+                o_data	 => partial_fir_out(i)
+		);
+    o_data(i)<= partial_fir_out(i)(cst_w_fir_adder_out-1 DOWNTO cst_w_fir_adder_out-cst_w_out);
+  END GENERATE partial_fir_for;
+
+
+END Simple_Fir;

utils.vhd

@@ -0,0 +1,33 @@
+-- *********************** Divers fonction utiles ***************************
+
+
+LIBRARY ieee; 
+USE ieee.std_logic_1164.ALL;
+
+
+PACKAGE utils IS
+  PROCEDURE horloge ( SIGNAL h: OUT std_logic; th, tb : time); 
+  PROCEDURE horloge_retard ( SIGNAL h : OUT std_logic; periode : time ;
+                             retard : time); 
+END utils;
+---------------------------------------------------
+PACKAGE BODY utils IS
+  PROCEDURE horloge ( SIGNAL h : OUT std_logic; th, tb : time) IS 
+  BEGIN 
+    LOOP 
+      h <= '0', '1' AFTER tb; 
+      WAIT FOR tb + th ; 
+    END LOOP; 
+  END;
+  
+  PROCEDURE horloge_retard ( SIGNAL h : OUT std_logic; periode : time ;
+                             retard : time) IS 
+  BEGIN 
+    h <= '0'; 
+    WAIT FOR retard; 
+    LOOP 
+      h <= '1' , '0' AFTER periode/2 ; 
+      WAIT FOR periode; 
+    END LOOP; 
+  END; 
+END utils;