From 1f9e608560bdaec0510069adfda9de47445afbcf Mon Sep 17 00:00:00 2001 From: Lilian RM Date: Wed, 29 Jul 2020 08:25:40 +0100 Subject: [PATCH] =?UTF-8?q?Transf=C3=A9rer=20les=20fichiers=20vers=20''?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- add_blk.vhd | 34 ++++++++++++++++++++++++++++++++++ partial_fir.vhd | 35 ++++++++--------------------------- poly_fir_pkg.vhd | 4 +++- 3 files changed, 45 insertions(+), 28 deletions(-) create mode 100644 add_blk.vhd diff --git a/add_blk.vhd b/add_blk.vhd new file mode 100644 index 0000000..0c59842 --- /dev/null +++ b/add_blk.vhd @@ -0,0 +1,34 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +USE work.POLY_FIR_PKG.ALL; + +ENTITY add_blk IS + GENERIC(w_out : IN natural); + PORT(i_clk : IN std_logic; + i_data1 : IN smpl_adder_generic; + i_data2 : IN smpl_adder_generic; + o_data : OUT smpl_fir_adder_data_out + ); +END add_blk; + +ARCHITECTURE add OF add_blk IS + + SIGNAL smpl_stages_out : smpl_adder_generic := (OTHERS => '0'); + +BEGIN -- ARCHITECTURE add + + -- purpose: creates the add process for the adding tree + -- type : sequential + -- inputs : i_clk, i_data1, i_data2 + -- outputs: o_data + adding_process : PROCESS (i_clk) IS + BEGIN -- PROCESS adding_process + IF rising_edge(i_clk) THEN -- rising clock edge + smpl_stages_out(w_out DOWNTO 0) <= std_logic_vector(unsigned(signed(i_data1(w_out-1)&i_data1(w_out-1 DOWNTO 0))+signed(i_data2(w_out-1)&i_data2(w_out-1 DOWNTO 0)))); + END IF; + END PROCESS adding_process; + + o_data <= smpl_stages_out; + +END ARCHITECTURE add; diff --git a/partial_fir.vhd b/partial_fir.vhd index 235493d..d053a76 100644 --- a/partial_fir.vhd +++ b/partial_fir.vhd @@ -19,18 +19,6 @@ ARCHITECTURE Adder_Tree OF PARTIAL_FIR IS SIGNAL vect_i_coeffs : vect_fir_coeffs_in; SIGNAL mult_out : vect_mult_data_out := (OTHERS => (OTHERS => '0')); - FUNCTION add ( - w_smpl : IN natural; - in1, in2 : IN smpl_adder_generic) - RETURN smpl_adder_generic IS - VARIABLE smpl_stages_out : smpl_adder_generic := (OTHERS => '0'); - VARIABLE isigned : smpl_adder_generic_signed; - BEGIN - isigned(w_smpl DOWNTO 0) := signed(in1(w_smpl-1)&in1(w_smpl-1 DOWNTO 0))+signed(in2(w_smpl-1)&in2(w_smpl-1 DOWNTO 0)); - smpl_stages_out(w_smpl DOWNTO 0) := std_logic_vector(unsigned(isigned(w_smpl DOWNTO 0))); - RETURN smpl_stages_out; - END FUNCTION; - BEGIN @@ -75,30 +63,23 @@ BEGIN -- -- inputs: matrix_adder_tree(0) -- outputs: matrix_adder_tree(cst_log2_adder_stages) - --tree_generation : PROCESS (i_clk) IS - --BEGIN -- PROCESS tree_generation - --IF(rising_edge(i_clk)) THEN stages_loop : FOR stage IN 1 TO cst_log2_adder_stages GENERATE cell_loops : FOR cell IN 0 TO 2**(cst_log2_adder_stages-stage)-1 GENERATE - matrix_adder_tree(stage)((2**stage)*cell) <= add(w_smpl => cst_w_mult_out+stage-1, in1 => matrix_adder_tree(stage-1)((2**(stage-1))*2*cell), in2 => matrix_adder_tree(stage-1)((2**(stage-1))*(2*cell+1))); + add_inst : ENTITY work.add_blk(add) + GENERIC MAP(w_out => cst_w_mult_out+stage-1) + PORT MAP(i_clk => i_clk, + i_data1 => matrix_adder_tree(stage-1)((2**(stage-1))*2*cell), + i_data2 => matrix_adder_tree(stage-1)((2**(stage-1))*(2*cell+1)), + o_data => matrix_adder_tree(stage)((2**stage)*cell) + ); END GENERATE cell_loops; END GENERATE stages_loop; - --END IF; - --END PROCESS tree_generation; - --stages_loop : FOR stage IN 1 TO cst_log2_adder_stages GENERATE - -- cell_loops : FOR cell IN 0 TO 2**(cst_log2_adder_stages-stage)-1 GENERATE - - -- matrix_adder_tree_signed(stage)((2**stage)*cell)(cst_w_mult_out+stage-1 DOWNTO 0) <= signed(matrix_adder_tree(stage-1)((2**stage)*cell)(cst_w_mult_out+stage-2)&matrix_adder_tree(stage-1)((2**stage)*cell)(cst_w_mult_out+stage-2 DOWNTO 0))+signed(matrix_adder_tree(stage-1)((2**(stage-1))*(2*cell+1))(cst_w_mult_out+stage-2)&matrix_adder_tree(stage-1)((2**(stage-1))*(2*cell+1))(cst_w_mult_out+stage-2 DOWNTO 0)); - -- matrix_adder_tree(stage)((2**stage)*cell)(cst_w_mult_out+stage-1 DOWNTO 0) <= std_logic_vector(unsigned(matrix_adder_tree_signed(stage)((2**stage)*cell)(cst_w_mult_out+stage-1 DOWNTO 0))); - - -- END GENERATE cell_loops; - --END GENERATE stages_loop; - -- take the result when adder tree finished +-- take the result when adder tree finished o_data <= matrix_adder_tree(cst_log2_adder_stages)(0); END Adder_Tree; diff --git a/poly_fir_pkg.vhd b/poly_fir_pkg.vhd index 2e07a09..ff14728 100644 --- a/poly_fir_pkg.vhd +++ b/poly_fir_pkg.vhd @@ -26,7 +26,6 @@ PACKAGE POLY_FIR_PKG IS -- ADC CONSTANT cst_w_in : natural := 6; -- ADC in bitwidth - CONSTANT cst_w_out : natural := 17; CONSTANT cst_nb_samples_adc_in : natural := 80; -- ADC in nb samples @@ -40,9 +39,12 @@ PACKAGE POLY_FIR_PKG IS CONSTANT cst_downsampling_factor : natural := 8; -- POLYPHASE FILTER CONSTANT cst_nb_subfilters : natural := 20; + -- -- CALCULATIONS -- -- + CONSTANT cst_w_out : natural := cst_w_in + cst_w_coeff+cst_log2_sup_nb_coeffs_subfilter_in; + -- SHIFT REG CONSTANT cst_nb_coeffs_subfilter_in : natural := cst_nb_coeffs_filter_in/cst_nb_subfilters;