Transférer les fichiers vers ''

poly_fir_tb.vhd

@@ -13,15 +13,15 @@ ENTITY poly_fir_tb IS
   GENERIC (
     demi_periode : time   := 5 ns;
 -- duree de la demi periode des horloges
-    test_e       : string := "D:\Stage\ALMA_OPFB\simu\polyphase_fir\tb_txts_files\input.txt";
+    test_e       : string := "D:\Stage\ALMA_OPFB\simu\polyphase_fir - v0.2\tb_txts_files\input.txt";
 -- fichier test contenant les echantillons d'entree
 
-    test_s : string := "D:\Stage\ALMA_OPFB\simu\polyphase_fir\tb_txts_files\output.txt"
+    test_s : string := "D:\Stage\ALMA_OPFB\simu\polyphase_fir - v0.2\tb_txts_files\output.txt"
 -- fichier contenant les echantillons de sortie
 
     --fir_addr : std_logic_vector(band5a_w_fc-1 DOWNTO 0) := std_logic_vector(unsigned(band5a_fc_index, band5a_w_fc))
 
+-- coeff de décimation
     );
 
 END poly_fir_tb;
@@ -39,6 +39,7 @@ ARCHITECTURE beh OF poly_fir_tb IS
   SIGNAL sortie_fir_sim      : matrix_fir_data_out           := (OTHERS => (OTHERS => (OTHERS => '0')));
   --SIGNAL coeffs_fir     : vect_fir_coeffs_in := ;
   SIGNAL sortie_fir_sim_vect : vect_from_matrix_fir_data_out := (OTHERS => (OTHERS => '0'));
+  SIGNAL verif               : donnee_sortie;
 
 
 BEGIN  -- ARCHITECTURE beh
@@ -48,11 +49,11 @@ BEGIN  -- ARCHITECTURE beh
   horloge_entree : horloge(h, demi_periode, demi_periode);
 
   sortie_fir_sim_process : PROCESS(sortie_fir_sim)
-    VARIABLE mots_lignes : natural := 10;
+    VARIABLE mots_lignes : natural := cst_nb_parallel_firs;
   BEGIN
     FOR k IN 0 TO mots_lignes-1 LOOP
       FOR j IN 0 TO cst_nb_subfilters-1 LOOP
-        sortie_fir_sim_vect(k*mots_lignes+j) <= sortie_fir_sim(j)(k);
+        sortie_fir_sim_vect(k*cst_nb_subfilters+j) <= sortie_fir_sim(j)(k);
       END LOOP;
     END LOOP;
   END PROCESS;
@@ -100,12 +101,12 @@ BEGIN  -- ARCHITECTURE beh
   test : PROCESS
     CONSTANT header     : natural := 1;    -- nombre de ligne d'en tête
     CONSTANT nbr_ech    : natural := 2000000;  --nombre d'echantillons d'entree dans le fichier test
-    CONSTANT mots_ligne : natural := 100;  -- nombre de mots par ligne dans le ficher
+    CONSTANT mots_ligne : natural := 200;  -- nombre de mots par ligne dans le ficher
     VARIABLE nbr_ligne  : natural := 10000;  -- nombre de lignes restant à lire dans le fichier                              
     VARIABLE i          : natural;
     VARIABLE donnee     : donnee_sortie;
     VARIABLE ligne      : line;
-    VARIABLE tempo      : natural := 5;
+    VARIABLE tempo      : natural := 8;
     VARIABLE sortie     : integer;
     VARIABLE head       : boolean := false;
   BEGIN  -- PROCESS test 
@@ -125,7 +126,8 @@ BEGIN  -- ARCHITECTURE beh
         read(ligne, donnee(k));
         sortie        := to_integer(signed(sortie_fir_sim_vect(k)));
         sortie_fir(k) <= std_logic_vector(to_signed(donnee(k), cst_w_out));
-        ASSERT sortie = donnee(k) REPORT "Valeur fir FAUSSE"
+        verif(k)      <= sortie - donnee(k);
+        ASSERT verif(k) = 0 REPORT "Valeur fir FAUSSE"
           SEVERITY error;
       --ASSERT sortie /= donnee(k) REPORT "OK"
       --  SEVERITY note;

poly_shift_reg2.vhd

@@ -0,0 +1,79 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE work.POLY_FIR_PKG.ALL;
+
+ENTITY POLY_SHIFT_REG IS
+  PORT(i_clk  : IN  std_logic;
+       i_data : IN  vect_adc_data_out;
+       o_data : OUT matrix3D_reg_data_out
+       );
+END POLY_SHIFT_REG;
+
+ARCHITECTURE Fill_Matrix OF POLY_SHIFT_REG IS
+
+  TYPE vect_i_data_temp IS ARRAY (0 TO cst_nb_subfilters-1) OF smpl_adc_data_in;
+  TYPE matrix_i_data_temp IS ARRAY (0 TO 1) OF vect_i_data_temp;
+  SIGNAL data_matrix : matrix3D_reg_data_out;
+  --SIGNAL data_temp     : vect_reg_data := (OTHERS =>(OTHERS => '0'));
+  SIGNAL data_temp   : matrix_reg_data := (OTHERS => (OTHERS => (OTHERS => '0')));
+  --VARIABLE reg_i_data_temp : vect_i_data_temp := (OTHERS => (OTHERS => '0'));
+
+BEGIN
+
+
+
+  -- purpose: fill a 3D matrix from a register. Each row is the input of the
+  -- input of a partial filter; each 2D matrix rows-columns is the input for a
+  -- subfilter
+  -- inputs:  reg_i_data_temp, i_data
+  -- outputs: data_temp (3D matrix of std_logic_vectors)
+  PROCESS (i_clk) IS
+    VARIABLE subfilter_nb      : natural            := 0;
+    VARIABLE data_subfilter_nb : natural            := 0;
+    VARIABLE reg_i_data_temp   : matrix_i_data_temp;
+  BEGIN  -- PROCESS
+    IF rising_edge(i_clk) THEN          -- rising clock edge
+
+
+
+      -- shifting the old samples towards data_temp(0)
+      FOR i IN 0 TO cst_nb_subfilters-1 LOOP
+        data_temp(i)(0 TO cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs-1) <= data_temp(i)(cst_nb_parallel_firs TO cst_nb_samples_shiftreg_temp_in-1);
+      END LOOP;  -- i
+
+
+
+      -- fill a temp 2D matrix for each subfilter (equivalent to filling a temp
+      -- vector for 1 filter)
+      parallel_fir_for : FOR parallel_fir_nb IN 0 TO cst_nb_parallel_firs-1 LOOP
+
+        FOR i IN 0 TO cst_nb_subfilters-1 LOOP
+          reg_i_data_temp(1) := reg_i_data_temp(0);
+        END LOOP;
+        fill_previous_content : FOR data_nb IN cst_downsampling_factor TO cst_nb_subfilters-1 LOOP
+          data_temp(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= reg_i_data_temp(1)(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters));
+        END LOOP fill_previous_content;  -- data_nb
+        fill_data_temp : FOR data_nb IN 0 TO cst_downsampling_factor-1 LOOP  -- fill data
+          data_temp(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters))(cst_nb_samples_shiftreg_temp_in-cst_nb_parallel_firs+parallel_fir_nb) <= i_data(cst_downsampling_factor*parallel_fir_nb+data_nb);
+          reg_i_data_temp(0)(cst_nb_subfilters-1-((cst_downsampling_factor*parallel_fir_nb+data_nb) MOD cst_nb_subfilters))                                                              := i_data(cst_downsampling_factor*parallel_fir_nb+data_nb);
+
+        END LOOP fill_data_temp;
+      END LOOP parallel_fir_for;  -- parallel_fir_nb
+
+      o_data <= data_matrix;
+
+    END IF;
+  END PROCESS;
+
+
+
+  -- purpose: wiring (filling the 3D out matrix) for each line, for each subfilter
+  third_dimension : FOR subfilter_nb IN 0 TO cst_nb_subfilters-1 GENERATE
+    second_dimension : FOR parallel_fir IN 0 TO cst_nb_parallel_firs-1 GENERATE
+      first_dimension : FOR data_nb IN 0 TO cst_nb_coeffs_subfilter_in-1 GENERATE
+        data_matrix(subfilter_nb)(parallel_fir)(data_nb) <= data_temp(subfilter_nb)(data_nb+parallel_fir);
+      END GENERATE first_dimension;  -- data_nb
+    END GENERATE second_dimension;  -- parallel_fir
+  END GENERATE third_dimension;  -- subfilter_nb
+
+END Fill_Matrix;