5ndft_vhdl/5k_DFT_pkg.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_signed.ALL;

-- NOTE:
-- The number of in/output samples must be a 2^n factor of 5, < 160

PACKAGE FIVEn_DFT_PKG IS

  CONSTANT cst_w_in_5ndft  : natural := 19;  -- input_bitwidth
  CONSTANT cst_w_out_5ndft : natural := 6;   -- output bitwidth, must be < 30

  CONSTANT cst_nb_samples_in_5ndft : natural := 20;  -- must be 5*n

  CONSTANT cst_w_precision_winograd5_coeffs_5ndft : natural := 8;  -- must be <= 32 and >= 3, sign bit included. Ideal is >= 8
  CONSTANT cst_w_precision_radix2_coeffs_5ndft    : natural := 8;  -- must be <= 32 and >= 3, sign bit included. Ideal is >= 8
  -- CALCULATIONS --

  CONSTANT cst_nb_parallel_winograd5 : natural := cst_nb_samples_in_5ndft/5;

  CONSTANT cst_log2_nb_parallel_winograd5 : natural := 2;  -- = log2(cst_nb_parallel_winograd5)
  CONSTANT cst_w_winograd_added           : natural := cst_w_precision_winograd5_coeffs_5ndft+6;  -- 6 is the number of addition stages in the winograd5 blk
  CONSTANT cst_w_radix2_added             : natural := cst_w_precision_radix2_coeffs_5ndft+2;
  CONSTANT cst_dft_w_out_5ndft            : natural := cst_w_in_5ndft+cst_w_winograd_added+(cst_log2_nb_parallel_winograd5*cst_w_radix2_added);
  CONSTANT cst_winograd5_w_out_5ndft      : natural := cst_w_in_5ndft+cst_w_winograd_added;  -- 6 is the number of addition stages in the winograd5 blk
  CONSTANT cst_nb_wn_coeffs               : natural := cst_nb_samples_in_5ndft/2;

  -- TYPES --

  SUBTYPE smpl_in_5ndft IS std_logic_vector(cst_w_in_5ndft-1 DOWNTO 0);
  SUBTYPE smpl_out_5ndft IS std_logic_vector(cst_w_out_5ndft-1 DOWNTO 0);

  TYPE vect_dft_input IS ARRAY (0 TO cst_nb_samples_in_5ndft-1) OF smpl_in_5ndft;
  TYPE vect_dft_output IS ARRAY (0 TO cst_nb_samples_in_5ndft-1) OF smpl_out_5ndft;
  -- winograd5
  SUBTYPE smpl_out_winograd5_5ndft IS std_logic_vector(cst_winograd5_w_out_5ndft-1 DOWNTO 0);
  SUBTYPE smpl_out_winograd5_signed_5ndft IS signed(cst_winograd5_w_out_5ndft-1 DOWNTO 0);

  TYPE vect_input_winograd5_5ndft IS ARRAY (0 TO 4) OF smpl_in_5ndft;
  TYPE vect_output_winograd5_5ndft IS ARRAY (0 TO 4) OF smpl_out_winograd5_5ndft;
  TYPE vect_total_output_winograd5_cells IS ARRAY (0 TO cst_nb_samples_in_5ndft-1) OF smpl_out_winograd5_5ndft;

  TYPE vect_winograd5_generic_stage IS ARRAY (0 TO 5) OF smpl_out_winograd5_5ndft;
  TYPE matrix_winograd5_generic_stages IS ARRAY (0 TO 7) OF vect_winograd5_generic_stage;

  SUBTYPE smpl_mult_factor_w_multipliers IS std_logic_vector(cst_w_precision_winograd5_coeffs_5ndft-1 DOWNTO 0);
  SUBTYPE smpl_mult_factor_w_multipliers_signed IS signed(cst_w_precision_winograd5_coeffs_5ndft-1 DOWNTO 0);
  TYPE vect_mult_factors_32b IS ARRAY (1 TO 5) OF std_logic_vector(31 DOWNTO 0);
  TYPE vect_mult_factor_w_multipliers IS ARRAY (1 TO 5) OF smpl_mult_factor_w_multipliers;

  --radix2
  SUBTYPE smpl_cos_sin_wb IS std_logic_vector(cst_w_precision_radix2_coeffs_5ndft-1 DOWNTO 0);
  SUBTYPE smpl_cos_sin_signed_wb IS signed(cst_w_precision_radix2_coeffs_5ndft-1 DOWNTO 0);
  TYPE vect_cos_sin_k_pi_over_5_32b IS ARRAY(0 TO 4) OF std_logic_vector(31 DOWNTO 0);
  TYPE vect_cos_sin_k_pi_over_5_wb IS ARRAY(0 TO 4) OF smpl_cos_sin_wb;
  TYPE vect_cos_sin_k_pi_over_80_32b IS ARRAY (0 TO cst_nb_wn_coeffs-1) OF std_logic_vector(31 DOWNTO 0);

  SUBTYPE smpl_out_radix2 IS std_logic_vector(cst_dft_w_out_5ndft-1 DOWNTO 0);
  SUBTYPE smpl_out_signed_radix2 IS signed(cst_dft_w_out_5ndft-1 DOWNTO 0);
  TYPE vect_radix2_fft_line IS ARRAY (0 TO cst_log2_nb_parallel_winograd5) OF smpl_out_radix2;
  TYPE vect_radix2_line IS ARRAY (0 TO 3) OF smpl_out_radix2;
  TYPE matrix_radix2_cell IS ARRAY (0 TO 1) OF vect_radix2_line;

  -- whole fft
  TYPE matrix_fft_stages IS ARRAY (0 TO cst_nb_samples_in_5ndft-1) OF vect_radix2_fft_line;  -- inputs and outputs of radix2 cells

END;